v 20081231 1
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data=2008-08-19 / 2009-05-15
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rev=v0.1.7j
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fname=../openarm/sdram.sch
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auth=Jelle de Jong <jelledejong@powercraft.nl>
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page=04
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pages=14
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tiltle=OpenARM SBC SDRAM Design
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company=PowerCraft Technology
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licence=GPLv3
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project=OpenARM SBC Project
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T 45900 55650 5 10 1 1 0 6 1
netname=RAM_DQM[0]
}
N 44400 55300 46000 55300 4
{
T 45900 55350 5 10 1 1 0 6 1
netname=RAM_DQM[1]
}
N 44400 56200 46000 56200 4
{
T 45900 56250 5 10 1 1 0 6 1
netname=RAM_CKE
}
N 44400 56500 46000 56500 4
{
T 45900 56550 5 10 1 1 0 6 1
netname=RAM_CLK
}
N 44400 54700 46000 54700 4
{
T 45900 54750 5 10 1 1 0 6 1
netname=RAM_CAS_N
}
N 44400 54400 46000 54400 4
{
T 45900 54450 5 10 1 1 0 6 1
netname=RAM_RAS_N
}
N 44400 53800 46000 53800 4
{
T 45900 53850 5 10 1 1 0 6 1
netname=RAM_WR_N
}
N 44400 53500 46000 53500 4
{
T 45900 53550 5 10 1 1 0 6 1
netname=RAM_CS_N
}
N 44100 45100 45800 45100 4
{
T 45400 45150 5 10 1 1 0 6 1
netname=RAM_DQM[2]
}
N 44100 44800 45800 44800 4
{
T 45400 44850 5 10 1 1 0 6 1
netname=RAM_DQM[3]
}
N 50600 45700 52000 45700 4
{
T 50900 45750 5 10 1 1 0 0 1
netname=RAM_D[16]
}
N 50600 45400 52000 45400 4
{
T 50900 45450 5 10 1 1 0 0 1
netname=RAM_D[17]
}
N 50600 45100 52000 45100 4
{
T 50900 45150 5 10 1 1 0 0 1
netname=RAM_D[18]
}
N 50600 44800 52000 44800 4
{
T 50900 44850 5 10 1 1 0 0 1
netname=RAM_D[19]
}
N 50600 44500 52000 44500 4
{
T 50900 44550 5 10 1 1 0 0 1
netname=RAM_D[20]
}
N 50600 44200 52000 44200 4
{
T 50900 44250 5 10 1 1 0 0 1
netname=RAM_D[21]
}
N 50600 43900 52000 43900 4
{
T 50900 43950 5 10 1 1 0 0 1
netname=RAM_D[22]
}
N 50600 43600 52000 43600 4
{
T 50900 43650 5 10 1 1 0 0 1
netname=RAM_D[23]
}
N 50600 43300 52000 43300 4
{
T 50900 43350 5 10 1 1 0 0 1
netname=RAM_D[24]
}
N 50600 43000 52000 43000 4
{
T 50900 43050 5 10 1 1 0 0 1
netname=RAM_D[25]
}
N 50600 42700 52000 42700 4
{
T 50900 42750 5 10 1 1 0 0 1
netname=RAM_D[26]
}
N 50600 42400 52000 42400 4
{
T 50900 42450 5 10 1 1 0 0 1
netname=RAM_D[27]
}
N 50600 42100 52000 42100 4
{
T 50900 42150 5 10 1 1 0 0 1
netname=RAM_D[28]
}
N 50600 41800 52000 41800 4
{
T 50900 41850 5 10 1 1 0 0 1
netname=RAM_D[29]
}
N 50600 41500 52000 41500 4
{
T 50900 41550 5 10 1 1 0 0 1
netname=RAM_D[30]
}
N 50600 41200 52000 41200 4
{
T 50900 41250 5 10 1 1 0 0 1
netname=RAM_D[31]
}
C 46000 51700 1 0 0 MT48LC16M16A2.sym
{
T 46300 62000 5 10 1 1 0 0 1
device=MT48LC16M16A2P-7E:D
T 46300 62200 5 10 1 1 0 0 1
footprint=TSOP-65P-640L1-54N__MICRON_MT48LC16M16A2P-7E
T 46300 62400 5 10 1 1 0 0 1
refdes=U401
}
C 59000 51700 1 0 0 MT48LC16M16A2.sym
{
T 59300 62000 5 10 1 1 0 0 1
device=MT48LC16M16A2P-7E:D
T 59300 62200 5 10 1 1 0 0 1
footprint=TSOP-65P-640L1-54N__MICRON_MT48LC16M16A2P-7E
T 59300 62400 5 10 1 1 0 0 1
refdes=U403
}
C 45800 40600 1 0 0 LPC3180-RAM.sym
{
T 50100 50900 5 10 1 1 0 6 1
block=VSS (RAM)
T 46300 50900 5 10 1 1 0 0 1
device=LPC3180FEL320
T 46300 51100 5 10 1 1 0 0 1
footprint=BGA320N50P4X4_1300X1300X90__NXP_LPC3180FEL320_SOT824
T 46300 51300 5 10 1 1 0 0 1
refdes=U001
}
C 66300 44700 1 0 0 LPC3180-VDD-RAM.sym
{
T 69800 48100 5 10 1 1 0 6 1
block=VSS (RAM)
T 66800 48100 5 10 1 1 0 0 1
device=LPC3180FEL320
T 66800 48300 5 10 1 1 0 0 1
footprint=BGA320N50P4X4_1300X1300X90__NXP_LPC3180FEL320_SOT824
T 66800 48500 5 10 1 1 0 0 1
refdes=U001
}
C 55600 44100 1 0 0 LPC3180-VSS-RAM.sym
{
T 59100 48100 5 10 1 1 0 6 1
block=VSS (RAM)
T 56100 48100 5 10 1 1 0 0 1
device=LPC3180FEL320
T 56100 48300 5 10 1 1 0 0 1
footprint=BGA320N50P4X4_1300X1300X90__NXP_LPC3180FEL320_SOT824
T 56100 48500 5 10 1 1 0 0 1
refdes=U001
}
C 55100 44200 1 0 0 gnd-1.sym
N 55600 47700 55200 47700 4
N 55200 47700 55200 44500 4
N 55600 44700 55200 44700 4
N 55600 45000 55200 45000 4
N 55600 45300 55200 45300 4
N 55600 45600 55200 45600 4
N 55600 45900 55200 45900 4
N 55600 46200 55200 46200 4
N 55600 46500 55200 46500 4
N 55600 46800 55200 46800 4
N 55600 47100 55200 47100 4
N 55600 47400 55200 47400 4
C 64900 46900 1 90 0 capacitor-1.sym
{
T 64200 47100 5 10 0 0 90 0 1
device=GRM21BR71H104KA01L
T 64400 47100 5 10 1 1 90 0 1
refdes=C420
T 64000 47100 5 10 0 0 90 0 1
symversion=0.1
T 64900 46900 5 10 0 0 90 0 1
footprint=0805
T 65000 47100 5 10 1 1 90 2 1
value=100nF
}
C 63800 46900 1 90 0 capacitor-1.sym
{
T 63100 47100 5 10 0 0 90 0 1
device=GRM21BR71H104KA01L
T 63300 47100 5 10 1 1 90 0 1
refdes=C418
T 62900 47100 5 10 0 0 90 0 1
symversion=0.1
T 63800 46900 5 10 0 0 90 0 1
footprint=0805
T 63900 47100 5 10 1 1 90 2 1
value=100nF
}
C 62700 46900 1 90 0 capacitor-1.sym
{
T 62000 47100 5 10 0 0 90 0 1
device=GRM21BR71H104KA01L
T 62200 47100 5 10 1 1 90 0 1
refdes=C416
T 61800 47100 5 10 0 0 90 0 1
symversion=0.1
T 62700 46900 5 10 0 0 90 0 1
footprint=0805
T 62800 47100 5 10 1 1 90 2 1
value=100nF
}
C 61600 46900 1 90 0 capacitor-1.sym
{
T 60900 47100 5 10 0 0 90 0 1
device=GRM21BR71H104KA01L
T 61100 47100 5 10 1 1 90 0 1
refdes=C414
T 60700 47100 5 10 0 0 90 0 1
symversion=0.1
T 61600 46900 5 10 0 0 90 0 1
footprint=0805
T 61700 47100 5 10 1 1 90 2 1
value=100nF
}
C 64900 43700 1 90 0 capacitor-1.sym
{
T 64200 43900 5 10 0 0 90 0 1
device=GRM21BR71H104KA01L
T 64400 43900 5 10 1 1 90 0 1
refdes=C423
T 64000 43900 5 10 0 0 90 0 1
symversion=0.1
T 64900 43700 5 10 0 0 90 0 1
footprint=0805
T 65000 43900 5 10 1 1 90 2 1
value=100nF
}
C 63800 43700 1 90 0 capacitor-1.sym
{
T 63100 43900 5 10 0 0 90 0 1
device=GRM21BR71H104KA01L
T 63300 43900 5 10 1 1 90 0 1
refdes=C422
T 62900 43900 5 10 0 0 90 0 1
symversion=0.1
T 63800 43700 5 10 0 0 90 0 1
footprint=0805
T 63900 43900 5 10 1 1 90 2 1
value=100nF
}
C 62700 43700 1 90 0 capacitor-1.sym
{
T 62000 43900 5 10 0 0 90 0 1
device=GRM21BR71H104KA01L
T 62200 43900 5 10 1 1 90 0 1
refdes=C421
T 61800 43900 5 10 0 0 90 0 1
symversion=0.1
T 62700 43700 5 10 0 0 90 0 1
footprint=0805
T 62800 43900 5 10 1 1 90 2 1
value=100nF
}
C 61600 43700 1 90 0 capacitor-1.sym
{
T 60900 43900 5 10 0 0 90 0 1
device=GRM21BR71H104KA01L
T 61100 43900 5 10 1 1 90 0 1
refdes=C419
T 60700 43900 5 10 0 0 90 0 1
symversion=0.1
T 61600 43700 5 10 0 0 90 0 1
footprint=0805
T 61700 43900 5 10 1 1 90 2 1
value=100nF
}
C 60500 43700 1 90 0 capacitor-1.sym
{
T 59800 43900 5 10 0 0 90 0 1
device=GRM21BR71H104KA01L
T 60000 43900 5 10 1 1 90 0 1
refdes=C417
T 59600 43900 5 10 0 0 90 0 1
symversion=0.1
T 60500 43700 5 10 0 0 90 0 1
footprint=0805
T 60600 43900 5 10 1 1 90 2 1
value=100nF
}
C 61300 46400 1 0 0 gnd-1.sym
N 61400 46900 61400 46700 4
C 62400 46400 1 0 0 gnd-1.sym
N 62500 46900 62500 46700 4
C 63500 46400 1 0 0 gnd-1.sym
N 63600 46900 63600 46700 4
C 64600 46400 1 0 0 gnd-1.sym
N 64700 46900 64700 46700 4
C 64600 43200 1 0 0 gnd-1.sym
N 64700 43700 64700 43500 4
C 63500 43200 1 0 0 gnd-1.sym
N 63600 43700 63600 43500 4
C 62400 43200 1 0 0 gnd-1.sym
N 62500 43700 62500 43500 4
C 61300 43200 1 0 0 gnd-1.sym
N 61400 43700 61400 43500 4
C 60200 43200 1 0 0 gnd-1.sym
N 60300 43700 60300 43500 4
N 63600 44600 63600 45000 4
N 61400 44600 61400 45400 4
N 60300 44600 60300 45600 4
N 62500 44600 62500 45200 4
N 64700 48000 65600 48000 4
N 63600 47800 63600 48200 4
N 62500 47800 62500 48400 4
N 61400 47800 61400 48600 4
N 61400 48600 66200 48600 4
N 66200 48600 66200 47700 4
N 62500 48400 66000 48400 4
N 66000 48400 66000 47400 4
N 63600 48200 65800 48200 4
N 65800 48200 65800 47100 4
N 65600 46800 65600 48000 4
N 65400 46500 65400 45600 4
N 60300 45600 65400 45600 4
N 65600 46200 65600 45400 4
N 61400 45400 65600 45400 4
N 62500 45200 65800 45200 4
N 66000 45600 66000 45000 4
N 63600 45000 66000 45000 4
N 65800 45900 65800 45200 4
N 66200 45300 66200 44800 4
N 64700 44800 66200 44800 4
N 66300 45300 66200 45300 4
N 66000 45600 66300 45600 4
N 65800 45900 66300 45900 4
N 65600 46200 66300 46200 4
N 65400 46500 66300 46500 4
N 65600 46800 66300 46800 4
N 65800 47100 66300 47100 4
N 66000 47400 66300 47400 4
N 66200 47700 66300 47700 4
C 64500 48800 1 0 0 generic-power.sym
{
T 64700 49050 5 10 1 1 0 3 1
net=+3.125V:1
}
C 64500 45800 1 0 0 generic-power.sym
{
T 64700 46050 5 10 1 1 0 3 1
net=+3.125V:1
}
N 64700 48800 64700 48600 4
N 64700 48600 64700 48400 4
N 64700 48400 64700 48200 4
N 64700 47800 64700 48200 4
N 64700 45800 64700 45600 4
N 64700 45600 64700 45400 4
N 64700 45400 64700 45200 4
N 64700 45200 64700 45000 4
N 64700 44600 64700 45000 4
N 44100 43300 45800 43300 4
{
T 45400 43350 5 10 1 1 0 6 1
netname=RAM_CLKIN
}
N 54600 56800 56300 56800 4
{
T 55900 56850 5 10 1 1 0 6 1
netname=RAM_CLKIN
}
C 56300 56700 1 0 0 resistor-2.sym
{
T 56700 57050 5 10 0 0 0 0 1
device=MC 0.1W 0805 0R
T 56500 57000 5 10 1 1 0 0 1
refdes=R402
T 56500 56600 5 10 1 1 0 2 1
value=0
T 56300 56700 5 10 0 1 0 0 1
footprint=0805
}
N 57200 56800 57700 56800 4
N 57700 56800 57700 56500 4
N 44700 56800 44700 56500 4
C 43300 56700 1 0 0 resistor-2.sym
{
T 43700 57050 5 10 0 0 0 0 1
device=MC 0.1W 0805 0R
T 43500 57000 5 10 1 1 0 0 1
refdes=R401
T 43500 56600 5 10 1 1 0 2 1
value=0
T 43300 56700 5 10 0 1 0 0 1
footprint=0805
}
N 41600 56800 43300 56800 4
{
T 42900 56850 5 10 1 1 0 6 1
netname=RAM_CLKIN
}
N 44200 56800 44700 56800 4