v 20060123 1 B 500 300 3800 9900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 T 4100 10300 9 10 0 0 0 0 1 uselicense=unlimited T 4100 10500 9 10 0 0 0 0 1 distlicense=GPL (v2 or any later version) T 4100 10700 9 10 0 0 0 0 1 copyright=2008 Tibor Palinkas T 4100 10900 9 10 0 0 0 0 1 author=Tibor Palinkas T 4100 11100 9 10 0 0 0 0 1 description=NXP 16/32-bit ARM926EJ-S microcontroller T 4100 11300 9 10 0 0 0 0 1 documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf T 4300 10300 5 10 1 1 0 6 1 block=RAM T 500 10300 5 10 1 1 0 0 1 device=LPC3180FEL320 T 500 10500 5 10 1 1 0 0 1 footprint=SOT824 T 500 10700 5 10 1 1 0 0 1 refdes=U? P 0 7200 500 7200 1 0 0 { T 550 7200 9 10 1 1 0 1 1 pinlabel=RAM_A[09] T 400 7250 5 8 1 1 0 6 1 pinnumber=AA23 T 400 7250 5 8 0 1 0 6 1 pinseq=AA23 } P 0 9900 500 9900 1 0 0 { T 550 9900 9 10 1 1 0 1 1 pinlabel=RAM_A[00] T 400 9950 5 8 1 1 0 6 1 pinnumber=AD22 T 400 9950 5 8 0 1 0 6 1 pinseq=AD22 } P 4800 3600 4300 3600 1 0 0 { T 4250 3600 9 10 1 1 0 7 1 pinlabel=RAM_D[21] T 4400 3650 5 8 1 1 0 0 1 pinnumber=H24 T 4400 3650 5 8 0 1 0 0 1 pinseq=H24 } P 0 6300 500 6300 1 0 0 { T 550 6300 9 10 1 1 0 1 1 pinlabel=RAM_A[12] T 400 6350 5 8 1 1 0 6 1 pinnumber=Y23 T 400 6350 5 8 0 1 0 6 1 pinseq=Y23 } P 0 3600 500 3600 1 0 0 { T 550 3600 9 10 1 1 0 1 1 pinlabel=RAM_CAS_N T 400 3650 5 8 1 1 0 6 1 pinnumber=V23 T 400 3650 5 8 0 1 0 6 1 pinseq=V23 } P 4800 2100 4300 2100 1 0 0 { T 4250 2100 9 10 1 1 0 7 1 pinlabel=RAM_D[26] T 4400 2150 5 8 1 1 0 0 1 pinnumber=H23 T 4400 2150 5 8 0 1 0 0 1 pinseq=H23 } P 4800 5700 4300 5700 1 0 0 { T 4250 5700 9 10 1 1 0 7 1 pinlabel=RAM_D[14] T 4400 5750 5 8 1 1 0 0 1 pinnumber=M23 T 4400 5750 5 8 0 1 0 0 1 pinseq=M23 } P 0 2700 500 2700 1 0 0 { T 550 2700 9 10 1 1 0 1 1 pinlabel=RAM_CLKIN T 400 2750 5 8 1 1 0 6 1 pinnumber=T21 T 400 2750 5 8 0 1 0 6 1 pinseq=T21 } P 4800 8400 4300 8400 1 0 0 { T 4250 8400 9 10 1 1 0 7 1 pinlabel=RAM_D[05] T 4400 8450 5 8 1 1 0 0 1 pinnumber=R23 T 4400 8450 5 8 0 1 0 0 1 pinseq=R23 } P 4800 9900 4300 9900 1 0 0 { T 4250 9900 9 10 1 1 0 7 1 pinlabel=RAM_D[00] T 4400 9950 5 8 1 1 0 0 1 pinnumber=T23 T 4400 9950 5 8 0 1 0 0 1 pinseq=T23 } P 0 6900 500 6900 1 0 0 { T 550 6900 9 10 1 1 0 1 1 pinlabel=RAM_A[10] T 400 6950 5 8 1 1 0 6 1 pinnumber=Y22 T 400 6950 5 8 0 1 0 6 1 pinseq=Y22 } P 0 4500 500 4500 1 0 0 { T 550 4500 9 10 1 1 0 1 1 pinlabel=RAM_DQM[2] T 400 4550 5 8 1 1 0 6 1 pinnumber=V21 T 400 4550 5 8 0 1 0 6 1 pinseq=V21 } P 4800 4200 4300 4200 1 0 0 { T 4250 4200 9 10 1 1 0 7 1 pinlabel=RAM_D[19] T 4400 4250 5 8 1 1 0 0 1 pinnumber=H21 T 4400 4250 5 8 0 1 0 0 1 pinseq=H21 } P 4800 600 4300 600 1 0 0 { T 4250 600 9 10 1 1 0 7 1 pinlabel=RAM_D[31] T 4400 650 5 8 1 1 0 0 1 pinnumber=E24 T 4400 650 5 8 0 1 0 0 1 pinseq=E24 } P 4800 8700 4300 8700 1 0 0 { T 4250 8700 9 10 1 1 0 7 1 pinlabel=RAM_D[04] T 4400 8750 5 8 1 1 0 0 1 pinnumber=P21 T 4400 8750 5 8 0 1 0 0 1 pinseq=P21 } P 4800 2400 4300 2400 1 0 0 { T 4250 2400 9 10 1 1 0 7 1 pinlabel=RAM_D[25] T 4400 2450 5 8 1 1 0 0 1 pinnumber=J21 T 4400 2450 5 8 0 1 0 0 1 pinseq=J21 } P 0 3300 500 3300 1 0 0 { T 550 3300 9 10 1 1 0 1 1 pinlabel=RAM_RAS_N T 400 3350 5 8 1 1 0 6 1 pinnumber=U21 T 400 3350 5 8 0 1 0 6 1 pinseq=U21 } P 0 6000 500 6000 1 0 0 { T 550 6000 9 10 1 1 0 1 1 pinlabel=RAM_A[13] T 400 6050 5 8 1 1 0 6 1 pinnumber=AA24 T 400 6050 5 8 0 1 0 6 1 pinseq=AA24 } P 4800 1200 4300 1200 1 0 0 { T 4250 1200 9 10 1 1 0 7 1 pinlabel=RAM_D[29] T 4400 1250 5 8 1 1 0 0 1 pinnumber=F21 T 4400 1250 5 8 0 1 0 0 1 pinseq=F21 } P 0 2100 500 2100 1 0 0 { T 550 2100 9 10 1 1 0 1 1 pinlabel=RAM_CKE T 400 2150 5 8 1 1 0 6 1 pinnumber=U24 T 400 2150 5 8 0 1 0 6 1 pinseq=U24 } P 0 2400 500 2400 1 0 0 { T 550 2400 9 10 1 1 0 1 1 pinlabel=RAM_CLK T 400 2450 5 8 1 1 0 6 1 pinnumber=U23 T 400 2450 5 8 0 1 0 6 1 pinseq=U23 } P 0 9000 500 9000 1 0 0 { T 550 9000 9 10 1 1 0 1 1 pinlabel=RAM_A[03] T 400 9050 5 8 1 1 0 6 1 pinnumber=AD24 T 400 9050 5 8 0 1 0 6 1 pinseq=AD24 } P 0 8700 500 8700 1 0 0 { T 550 8700 9 10 1 1 0 1 1 pinlabel=RAM_A[04] T 400 8750 5 8 1 1 0 6 1 pinnumber=AC22 T 400 8750 5 8 0 1 0 6 1 pinseq=AC22 } P 4800 2700 4300 2700 1 0 0 { T 4250 2700 9 10 1 1 0 7 1 pinlabel=RAM_D[24] T 4400 2750 5 8 1 1 0 0 1 pinnumber=G23 T 4400 2750 5 8 0 1 0 0 1 pinseq=G23 } P 4800 5400 4300 5400 1 0 0 { T 4250 5400 9 10 1 1 0 7 1 pinlabel=RAM_D[15] T 4400 5450 5 8 1 1 0 0 1 pinnumber=L24 T 4400 5450 5 8 0 1 0 0 1 pinseq=L24 } P 0 4200 500 4200 1 0 0 { T 550 4200 9 10 1 1 0 1 1 pinlabel=RAM_DQM[3] T 400 4250 5 8 1 1 0 6 1 pinnumber=W24 T 400 4250 5 8 0 1 0 6 1 pinseq=W24 } P 4800 900 4300 900 1 0 0 { T 4250 900 9 10 1 1 0 7 1 pinlabel=RAM_D[30] T 4400 950 5 8 1 1 0 0 1 pinnumber=E23 T 4400 950 5 8 0 1 0 0 1 pinseq=E23 } P 4800 7800 4300 7800 1 0 0 { T 4250 7800 9 10 1 1 0 7 1 pinlabel=RAM_D[08] T 4400 7850 5 8 1 1 0 0 1 pinnumber=P23 T 4400 7850 5 8 0 1 0 0 1 pinseq=P23 } P 0 7800 500 7800 1 0 0 { T 550 7800 9 10 1 1 0 1 1 pinlabel=RAM_A[07] T 400 7850 5 8 1 1 0 6 1 pinnumber=AB22 T 400 7850 5 8 0 1 0 6 1 pinseq=AB22 } P 4800 6000 4300 6000 1 0 0 { T 4250 6000 9 10 1 1 0 7 1 pinlabel=RAM_D[13] T 4400 6050 5 8 1 1 0 0 1 pinnumber=L22 T 4400 6050 5 8 0 1 0 0 1 pinseq=L22 } P 4800 7500 4300 7500 1 0 0 { T 4250 7500 9 10 1 1 0 7 1 pinlabel=RAM_D[07] T 4400 7550 5 8 1 1 0 0 1 pinnumber=N21 T 4400 7550 5 8 0 1 0 0 1 pinseq=N21 } P 4800 9300 4300 9300 1 0 0 { T 4250 9300 9 10 1 1 0 7 1 pinlabel=RAM_D[02] T 4400 9350 5 8 1 1 0 0 1 pinnumber=T24 T 4400 9350 5 8 0 1 0 0 1 pinseq=T24 } P 0 5100 500 5100 1 0 0 { T 550 5100 9 10 1 1 0 1 1 pinlabel=RAM_DQM[0] T 400 5150 5 8 1 1 0 6 1 pinnumber=Y24 T 400 5150 5 8 0 1 0 6 1 pinseq=Y24 } P 0 5700 500 5700 1 0 0 { T 550 5700 9 10 1 1 0 1 1 pinlabel=RAM_A[14] T 400 5750 5 8 1 1 0 6 1 pinnumber=W21 T 400 5750 5 8 0 1 0 6 1 pinseq=W21 } P 4800 6300 4300 6300 1 0 0 { T 4250 6300 9 10 1 1 0 7 1 pinlabel=RAM_D[12] T 4400 6350 5 8 1 1 0 0 1 pinnumber=M24 T 4400 6350 5 8 0 1 0 0 1 pinseq=M24 } P 4800 1800 4300 1800 1 0 0 { T 4250 1800 9 10 1 1 0 7 1 pinlabel=RAM_D[27] T 4400 1850 5 8 1 1 0 0 1 pinnumber=G24 T 4400 1850 5 8 0 1 0 0 1 pinseq=G24 } P 0 8400 500 8400 1 0 0 { T 550 8400 9 10 1 1 0 1 1 pinlabel=RAM_A[05] T 400 8450 5 8 1 1 0 6 1 pinnumber=AA21 T 400 8450 5 8 0 1 0 6 1 pinseq=AA21 } P 4800 5100 4300 5100 1 0 0 { T 4250 5100 9 10 1 1 0 7 1 pinlabel=RAM_D[16]/DDR_DQS0 T 4400 5150 5 8 1 1 0 0 1 pinnumber=L23 T 4400 5150 5 8 0 1 0 0 1 pinseq=L23 } P 4800 9000 4300 9000 1 0 0 { T 4250 9000 9 10 1 1 0 7 1 pinlabel=RAM_D[03] T 4400 9050 5 8 1 1 0 0 1 pinnumber=R24 T 4400 9050 5 8 0 1 0 0 1 pinseq=R24 } P 0 9600 500 9600 1 0 0 { T 550 9600 9 10 1 1 0 1 1 pinlabel=RAM_A[01] T 400 9650 5 8 1 1 0 6 1 pinnumber=AB20 T 400 9650 5 8 0 1 0 6 1 pinseq=AB20 } P 4800 1500 4300 1500 1 0 0 { T 4250 1500 9 10 1 1 0 7 1 pinlabel=RAM_D[28] T 4400 1550 5 8 1 1 0 0 1 pinnumber=F24 T 4400 1550 5 8 0 1 0 0 1 pinseq=F24 } P 0 8100 500 8100 1 0 0 { T 550 8100 9 10 1 1 0 1 1 pinlabel=RAM_A[06] T 400 8150 5 8 1 1 0 6 1 pinnumber=AC23 T 400 8150 5 8 0 1 0 6 1 pinseq=AC23 } P 4800 6600 4300 6600 1 0 0 { T 4250 6600 9 10 1 1 0 7 1 pinlabel=RAM_D[11] T 4400 6650 5 8 1 1 0 0 1 pinnumber=N23 T 4400 6650 5 8 0 1 0 0 1 pinseq=N23 } P 4800 7200 4300 7200 1 0 0 { T 4250 7200 9 10 1 1 0 7 1 pinlabel=RAM_D[09] T 4400 7250 5 8 1 1 0 0 1 pinnumber=N24 T 4400 7250 5 8 0 1 0 0 1 pinseq=N24 } P 0 9300 500 9300 1 0 0 { T 550 9300 9 10 1 1 0 1 1 pinlabel=RAM_A[02] T 400 9350 5 8 1 1 0 6 1 pinnumber=AD23 T 400 9350 5 8 0 1 0 6 1 pinseq=AD23 } P 0 4800 500 4800 1 0 0 { T 550 4800 9 10 1 1 0 1 1 pinlabel=RAM_DQM[1] T 400 4850 5 8 1 1 0 6 1 pinnumber=W23 T 400 4850 5 8 0 1 0 6 1 pinseq=W23 } P 4800 6900 4300 6900 1 0 0 { T 4250 6900 9 10 1 1 0 7 1 pinlabel=RAM_D[10] T 4400 6950 5 8 1 1 0 0 1 pinnumber=M22 T 4400 6950 5 8 0 1 0 0 1 pinseq=M22 } P 4800 4500 4300 4500 1 0 0 { T 4250 4500 9 10 1 1 0 7 1 pinlabel=RAM_D[18]/DDR_NCLK T 4400 4550 5 8 1 1 0 0 1 pinnumber=K24 T 4400 4550 5 8 0 1 0 0 1 pinseq=K24 } P 4800 3900 4300 3900 1 0 0 { T 4250 3900 9 10 1 1 0 7 1 pinlabel=RAM_D[20] T 4400 3950 5 8 1 1 0 0 1 pinnumber=J24 T 4400 3950 5 8 0 1 0 0 1 pinseq=J24 } P 0 7500 500 7500 1 0 0 { T 550 7500 9 10 1 1 0 1 1 pinlabel=RAM_A[08] T 400 7550 5 8 1 1 0 6 1 pinnumber=AB23 T 400 7550 5 8 0 1 0 6 1 pinseq=AB23 } P 0 6600 500 6600 1 0 0 { T 550 6600 9 10 1 1 0 1 1 pinlabel=RAM_A[11] T 400 6650 5 8 1 1 0 6 1 pinnumber=AB24 T 400 6650 5 8 0 1 0 6 1 pinseq=AB24 } P 4800 3000 4300 3000 1 0 0 { T 4250 3000 9 10 1 1 0 7 1 pinlabel=RAM_D[23] T 4400 3050 5 8 1 1 0 0 1 pinnumber=H22 T 4400 3050 5 8 0 1 0 0 1 pinseq=H22 } P 0 1200 500 1200 1 0 0 { T 550 1200 9 10 1 1 0 1 1 pinlabel=RAM_CS_N T 400 1250 5 8 1 1 0 6 1 pinnumber=V24 T 400 1250 5 8 0 1 0 6 1 pinseq=V24 } P 4800 4800 4300 4800 1 0 0 { T 4250 4800 9 10 1 1 0 7 1 pinlabel=RAM_D[17]/DDR_DQS1 T 4400 4850 5 8 1 1 0 0 1 pinnumber=L21 T 4400 4850 5 8 0 1 0 0 1 pinseq=L21 } P 4800 8100 4300 8100 1 0 0 { T 4250 8100 9 10 1 1 0 7 1 pinlabel=RAM_D[06] T 4400 8150 5 8 1 1 0 0 1 pinnumber=P24 T 4400 8150 5 8 0 1 0 0 1 pinseq=P24 } P 4800 9600 4300 9600 1 0 0 { T 4250 9600 9 10 1 1 0 7 1 pinlabel=RAM_D[01] T 4400 9650 5 8 1 1 0 0 1 pinnumber=T22 T 4400 9650 5 8 0 1 0 0 1 pinseq=T22 } P 4800 3300 4300 3300 1 0 0 { T 4250 3300 9 10 1 1 0 7 1 pinlabel=RAM_D[22] T 4400 3350 5 8 1 1 0 0 1 pinnumber=K23 T 4400 3350 5 8 0 1 0 0 1 pinseq=K23 } P 0 1500 500 1500 1 0 0 { T 550 1500 9 10 1 1 0 1 1 pinlabel=RAM_WR_N T 400 1550 5 8 1 1 0 6 1 pinnumber=V22 T 400 1550 5 8 0 1 0 6 1 pinseq=V22 }