Rev 310 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
120 | jelle | 1 | v 20080127 1 |
2 | C 40000 40000 0 0 0 title-bordered-A1.sym |
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174 | jelle | 3 | T 65900 40900 8 10 1 1 0 0 1 |
4 | data=2008-08-19 |
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5 | T 69800 40600 8 10 1 1 0 0 1 |
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338 | jelle | 6 | rev=v0.1.6j |
174 | jelle | 7 | T 65900 40600 8 10 1 1 0 0 1 |
8 | fname=../openarm/sdram.sch |
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9 | T 68800 41150 8 10 1 1 0 0 1 |
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10 | auth=Jelle de Jong <jelledejong@powercraft.nl> |
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11 | T 65900 40300 8 10 1 1 0 0 1 |
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12 | page=04 |
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13 | T 67400 40300 8 10 1 1 0 0 1 |
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267 | jelle | 14 | pages=14 |
174 | jelle | 15 | T 65400 41150 8 10 1 1 0 0 1 |
16 | tiltle=OpenARM SBC SDRAM Design |
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17 | T 68800 41400 8 10 1 1 0 0 1 |
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18 | company=PowerCraft Technology |
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19 | T 68800 40900 8 10 1 1 0 0 1 |
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20 | licence=GPLv3 |
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21 | T 69850 40300 8 10 1 1 0 0 1 |
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22 | project=OpenARM SBC Project |
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158 | jelle | 23 | N 61900 54100 62200 54100 4 |
24 | N 62200 53800 61900 53800 4 |
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25 | N 61900 53500 62200 53500 4 |
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26 | N 61900 53200 62200 53200 4 |
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27 | N 61900 52900 62200 52900 4 |
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28 | N 61900 52600 62200 52600 4 |
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29 | N 61900 52300 62200 52300 4 |
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30 | C 62100 51800 1 0 0 gnd-1.sym |
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31 | N 62200 52100 62200 54100 4 |
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32 | C 63100 53500 1 90 0 capacitor-1.sym |
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120 | jelle | 33 | { |
158 | jelle | 34 | T 62400 53700 5 10 0 0 90 0 1 |
267 | jelle | 35 | device=GRM21BR71H104KA01L |
158 | jelle | 36 | T 62600 53700 5 10 1 1 90 0 1 |
123 | jelle | 37 | refdes=C408 |
158 | jelle | 38 | T 62200 53700 5 10 0 0 90 0 1 |
120 | jelle | 39 | symversion=0.1 |
158 | jelle | 40 | T 63100 53500 5 10 0 0 90 0 1 |
120 | jelle | 41 | footprint=0805 |
158 | jelle | 42 | T 63200 53700 5 10 1 1 90 2 1 |
120 | jelle | 43 | value=100nF |
44 | } |
||
158 | jelle | 45 | C 64100 53500 1 90 0 capacitor-1.sym |
120 | jelle | 46 | { |
158 | jelle | 47 | T 63400 53700 5 10 0 0 90 0 1 |
267 | jelle | 48 | device=GRM21BR71H104KA01L |
158 | jelle | 49 | T 63600 53700 5 10 1 1 90 0 1 |
123 | jelle | 50 | refdes=C409 |
158 | jelle | 51 | T 63200 53700 5 10 0 0 90 0 1 |
120 | jelle | 52 | symversion=0.1 |
158 | jelle | 53 | T 64100 53500 5 10 0 0 90 0 1 |
120 | jelle | 54 | footprint=0805 |
158 | jelle | 55 | T 64200 53700 5 10 1 1 90 2 1 |
120 | jelle | 56 | value=100nF |
57 | } |
||
158 | jelle | 58 | C 65100 53500 1 90 0 capacitor-1.sym |
120 | jelle | 59 | { |
158 | jelle | 60 | T 64400 53700 5 10 0 0 90 0 1 |
267 | jelle | 61 | device=GRM21BR71H104KA01L |
158 | jelle | 62 | T 64600 53700 5 10 1 1 90 0 1 |
123 | jelle | 63 | refdes=C410 |
158 | jelle | 64 | T 64200 53700 5 10 0 0 90 0 1 |
120 | jelle | 65 | symversion=0.1 |
158 | jelle | 66 | T 65100 53500 5 10 0 0 90 0 1 |
120 | jelle | 67 | footprint=0805 |
158 | jelle | 68 | T 65200 53700 5 10 1 1 90 2 1 |
120 | jelle | 69 | value=100nF |
70 | } |
||
158 | jelle | 71 | C 66100 53500 1 90 0 capacitor-1.sym |
120 | jelle | 72 | { |
158 | jelle | 73 | T 65400 53700 5 10 0 0 90 0 1 |
267 | jelle | 74 | device=GRM21BR71H104KA01L |
158 | jelle | 75 | T 65600 53700 5 10 1 1 90 0 1 |
123 | jelle | 76 | refdes=C411 |
158 | jelle | 77 | T 65200 53700 5 10 0 0 90 0 1 |
120 | jelle | 78 | symversion=0.1 |
158 | jelle | 79 | T 66100 53500 5 10 0 0 90 0 1 |
120 | jelle | 80 | footprint=0805 |
158 | jelle | 81 | T 66200 53700 5 10 1 1 90 2 1 |
120 | jelle | 82 | value=100nF |
83 | } |
||
158 | jelle | 84 | N 61900 56500 62900 56500 4 |
85 | N 61900 56200 63900 56200 4 |
||
86 | N 63900 56200 63900 54400 4 |
||
87 | N 61900 55900 64900 55900 4 |
||
88 | N 64900 55900 64900 54400 4 |
||
89 | N 61900 55600 65900 55600 4 |
||
90 | N 65900 55600 65900 54400 4 |
||
91 | C 67100 53500 1 90 0 capacitor-1.sym |
||
120 | jelle | 92 | { |
158 | jelle | 93 | T 66400 53700 5 10 0 0 90 0 1 |
267 | jelle | 94 | device=GRM21BR71H104KA01L |
158 | jelle | 95 | T 66600 53700 5 10 1 1 90 0 1 |
123 | jelle | 96 | refdes=C412 |
158 | jelle | 97 | T 66200 53700 5 10 0 0 90 0 1 |
120 | jelle | 98 | symversion=0.1 |
158 | jelle | 99 | T 67100 53500 5 10 0 0 90 0 1 |
120 | jelle | 100 | footprint=0805 |
158 | jelle | 101 | T 67200 53700 5 10 1 1 90 2 1 |
120 | jelle | 102 | value=100nF |
103 | } |
||
158 | jelle | 104 | N 61900 55300 66900 55300 4 |
105 | N 66900 55300 66900 54400 4 |
||
106 | C 68100 53500 1 90 0 capacitor-1.sym |
||
120 | jelle | 107 | { |
158 | jelle | 108 | T 67400 53700 5 10 0 0 90 0 1 |
267 | jelle | 109 | device=GRM21BR71H104KA01L |
158 | jelle | 110 | T 67600 53700 5 10 1 1 90 0 1 |
123 | jelle | 111 | refdes=C413 |
158 | jelle | 112 | T 67200 53700 5 10 0 0 90 0 1 |
120 | jelle | 113 | symversion=0.1 |
158 | jelle | 114 | T 68100 53500 5 10 0 0 90 0 1 |
120 | jelle | 115 | footprint=0805 |
158 | jelle | 116 | T 68200 53700 5 10 1 1 90 2 1 |
120 | jelle | 117 | value=100nF |
118 | } |
||
158 | jelle | 119 | C 69100 53500 1 90 0 capacitor-1.sym |
120 | jelle | 120 | { |
158 | jelle | 121 | T 68400 53700 5 10 0 0 90 0 1 |
267 | jelle | 122 | device=GRM21BR71H104KA01L |
158 | jelle | 123 | T 68600 53700 5 10 1 1 90 0 1 |
124 | refdes=C415 |
||
125 | T 68200 53700 5 10 0 0 90 0 1 |
||
120 | jelle | 126 | symversion=0.1 |
158 | jelle | 127 | T 69100 53500 5 10 0 0 90 0 1 |
120 | jelle | 128 | footprint=0805 |
158 | jelle | 129 | T 69200 53700 5 10 1 1 90 2 1 |
120 | jelle | 130 | value=100nF |
131 | } |
||
158 | jelle | 132 | N 61900 55000 67900 55000 4 |
133 | N 67900 55000 67900 54400 4 |
||
134 | N 61900 54700 68900 54700 4 |
||
135 | N 68900 54700 68900 54400 4 |
||
136 | C 62800 53000 1 0 0 gnd-1.sym |
||
137 | N 62900 53500 62900 53300 4 |
||
138 | N 63900 53500 63900 53300 4 |
||
139 | C 63800 53000 1 0 0 gnd-1.sym |
||
140 | N 64900 53500 64900 53300 4 |
||
141 | C 64800 53000 1 0 0 gnd-1.sym |
||
142 | N 65900 53500 65900 53300 4 |
||
143 | C 65800 53000 1 0 0 gnd-1.sym |
||
144 | N 66900 53500 66900 53300 4 |
||
145 | C 66800 53000 1 0 0 gnd-1.sym |
||
146 | N 67900 53500 67900 53300 4 |
||
147 | C 67800 53000 1 0 0 gnd-1.sym |
||
148 | N 68900 53500 68900 53300 4 |
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149 | C 68800 53000 1 0 0 gnd-1.sym |
||
150 | C 62700 56500 1 0 0 generic-power.sym |
||
120 | jelle | 151 | { |
158 | jelle | 152 | T 62900 56750 5 10 1 1 0 3 1 |
120 | jelle | 153 | net=+3.125V:1 |
154 | } |
||
158 | jelle | 155 | N 62900 56200 62900 56500 4 |
156 | N 62900 56200 62900 55900 4 |
||
157 | N 62900 55900 62900 55600 4 |
||
158 | N 62900 55600 62900 55300 4 |
||
159 | N 62900 55300 62900 55000 4 |
||
160 | N 62900 55000 62900 54700 4 |
||
161 | N 62900 54700 62900 54400 4 |
||
162 | N 61900 61600 63225 61600 4 |
||
120 | jelle | 163 | { |
158 | jelle | 164 | T 62000 61650 5 10 1 1 0 0 1 |
123 | jelle | 165 | netname=RAM_D[16] |
120 | jelle | 166 | } |
158 | jelle | 167 | N 61900 61300 63225 61300 4 |
120 | jelle | 168 | { |
158 | jelle | 169 | T 62000 61350 5 10 1 1 0 0 1 |
123 | jelle | 170 | netname=RAM_D[17] |
120 | jelle | 171 | } |
158 | jelle | 172 | N 61900 61000 63225 61000 4 |
120 | jelle | 173 | { |
158 | jelle | 174 | T 62000 61050 5 10 1 1 0 0 1 |
123 | jelle | 175 | netname=RAM_D[18] |
120 | jelle | 176 | } |
158 | jelle | 177 | N 61900 60700 63225 60700 4 |
120 | jelle | 178 | { |
158 | jelle | 179 | T 62000 60750 5 10 1 1 0 0 1 |
123 | jelle | 180 | netname=RAM_D[19] |
120 | jelle | 181 | } |
158 | jelle | 182 | N 61900 60400 63225 60400 4 |
120 | jelle | 183 | { |
158 | jelle | 184 | T 62000 60450 5 10 1 1 0 0 1 |
123 | jelle | 185 | netname=RAM_D[20] |
120 | jelle | 186 | } |
158 | jelle | 187 | N 61900 60100 63225 60100 4 |
120 | jelle | 188 | { |
158 | jelle | 189 | T 62000 60150 5 10 1 1 0 0 1 |
123 | jelle | 190 | netname=RAM_D[21] |
120 | jelle | 191 | } |
158 | jelle | 192 | N 61900 59800 63225 59800 4 |
120 | jelle | 193 | { |
158 | jelle | 194 | T 62000 59850 5 10 1 1 0 0 1 |
123 | jelle | 195 | netname=RAM_D[22] |
120 | jelle | 196 | } |
158 | jelle | 197 | N 61900 59500 63225 59500 4 |
120 | jelle | 198 | { |
158 | jelle | 199 | T 62000 59550 5 10 1 1 0 0 1 |
123 | jelle | 200 | netname=RAM_D[23] |
120 | jelle | 201 | } |
158 | jelle | 202 | N 61900 59200 63225 59200 4 |
120 | jelle | 203 | { |
158 | jelle | 204 | T 62000 59250 5 10 1 1 0 0 1 |
123 | jelle | 205 | netname=RAM_D[24] |
120 | jelle | 206 | } |
158 | jelle | 207 | N 61900 58900 63225 58900 4 |
120 | jelle | 208 | { |
158 | jelle | 209 | T 62000 58950 5 10 1 1 0 0 1 |
123 | jelle | 210 | netname=RAM_D[25] |
120 | jelle | 211 | } |
158 | jelle | 212 | N 61900 58600 63225 58600 4 |
120 | jelle | 213 | { |
158 | jelle | 214 | T 62000 58650 5 10 1 1 0 0 1 |
123 | jelle | 215 | netname=RAM_D[26] |
120 | jelle | 216 | } |
158 | jelle | 217 | N 61900 58300 63225 58300 4 |
120 | jelle | 218 | { |
158 | jelle | 219 | T 62000 58350 5 10 1 1 0 0 1 |
123 | jelle | 220 | netname=RAM_D[27] |
120 | jelle | 221 | } |
158 | jelle | 222 | N 61900 58000 63225 58000 4 |
120 | jelle | 223 | { |
158 | jelle | 224 | T 62000 58050 5 10 1 1 0 0 1 |
123 | jelle | 225 | netname=RAM_D[28] |
120 | jelle | 226 | } |
158 | jelle | 227 | N 61900 57700 63225 57700 4 |
120 | jelle | 228 | { |
158 | jelle | 229 | T 62000 57750 5 10 1 1 0 0 1 |
123 | jelle | 230 | netname=RAM_D[29] |
120 | jelle | 231 | } |
158 | jelle | 232 | N 61900 57400 63225 57400 4 |
120 | jelle | 233 | { |
158 | jelle | 234 | T 62000 57450 5 10 1 1 0 0 1 |
123 | jelle | 235 | netname=RAM_D[30] |
120 | jelle | 236 | } |
158 | jelle | 237 | N 61900 57100 63225 57100 4 |
120 | jelle | 238 | { |
158 | jelle | 239 | T 62000 57150 5 10 1 1 0 0 1 |
123 | jelle | 240 | netname=RAM_D[31] |
120 | jelle | 241 | } |
158 | jelle | 242 | N 59000 61600 57600 61600 4 |
120 | jelle | 243 | { |
158 | jelle | 244 | T 58900 61650 5 10 1 1 0 6 1 |
120 | jelle | 245 | netname=RAM_A[00] |
246 | } |
||
158 | jelle | 247 | N 59000 61300 57600 61300 4 |
120 | jelle | 248 | { |
158 | jelle | 249 | T 58900 61350 5 10 1 1 0 6 1 |
120 | jelle | 250 | netname=RAM_A[01] |
251 | } |
||
158 | jelle | 252 | N 59000 61000 57600 61000 4 |
120 | jelle | 253 | { |
158 | jelle | 254 | T 58900 61050 5 10 1 1 0 6 1 |
120 | jelle | 255 | netname=RAM_A[02] |
256 | } |
||
158 | jelle | 257 | N 59000 60700 57600 60700 4 |
120 | jelle | 258 | { |
158 | jelle | 259 | T 58900 60750 5 10 1 1 0 6 1 |
120 | jelle | 260 | netname=RAM_A[03] |
261 | } |
||
158 | jelle | 262 | N 59000 60400 57600 60400 4 |
120 | jelle | 263 | { |
158 | jelle | 264 | T 58900 60450 5 10 1 1 0 6 1 |
120 | jelle | 265 | netname=RAM_A[04] |
266 | } |
||
158 | jelle | 267 | N 59000 60100 57600 60100 4 |
120 | jelle | 268 | { |
158 | jelle | 269 | T 58900 60150 5 10 1 1 0 6 1 |
120 | jelle | 270 | netname=RAM_A[05] |
271 | } |
||
158 | jelle | 272 | N 59000 59800 57600 59800 4 |
120 | jelle | 273 | { |
158 | jelle | 274 | T 58900 59850 5 10 1 1 0 6 1 |
120 | jelle | 275 | netname=RAM_A[06] |
276 | } |
||
158 | jelle | 277 | N 59000 59500 57600 59500 4 |
120 | jelle | 278 | { |
158 | jelle | 279 | T 58900 59550 5 10 1 1 0 6 1 |
120 | jelle | 280 | netname=RAM_A[07] |
281 | } |
||
158 | jelle | 282 | N 59000 59200 57600 59200 4 |
120 | jelle | 283 | { |
158 | jelle | 284 | T 58900 59250 5 10 1 1 0 6 1 |
120 | jelle | 285 | netname=RAM_A[08] |
286 | } |
||
158 | jelle | 287 | N 59000 58900 57600 58900 4 |
120 | jelle | 288 | { |
158 | jelle | 289 | T 58900 58950 5 10 1 1 0 6 1 |
120 | jelle | 290 | netname=RAM_A[09] |
291 | } |
||
158 | jelle | 292 | N 59000 58600 57600 58600 4 |
120 | jelle | 293 | { |
158 | jelle | 294 | T 58900 58650 5 10 1 1 0 6 1 |
120 | jelle | 295 | netname=RAM_A[10] |
296 | } |
||
158 | jelle | 297 | N 59000 58300 57600 58300 4 |
120 | jelle | 298 | { |
158 | jelle | 299 | T 58900 58350 5 10 1 1 0 6 1 |
120 | jelle | 300 | netname=RAM_A[11] |
301 | } |
||
158 | jelle | 302 | N 59000 58000 57600 58000 4 |
120 | jelle | 303 | { |
158 | jelle | 304 | T 58900 58050 5 10 1 1 0 6 1 |
120 | jelle | 305 | netname=RAM_A[12] |
306 | } |
||
158 | jelle | 307 | N 59000 57400 57600 57400 4 |
120 | jelle | 308 | { |
158 | jelle | 309 | T 58900 57450 5 10 1 1 0 6 1 |
120 | jelle | 310 | netname=RAM_A[13] |
311 | } |
||
158 | jelle | 312 | N 59000 57100 57600 57100 4 |
120 | jelle | 313 | { |
158 | jelle | 314 | T 58900 57150 5 10 1 1 0 6 1 |
120 | jelle | 315 | netname=RAM_A[14] |
316 | } |
||
158 | jelle | 317 | N 57400 55600 59000 55600 4 |
120 | jelle | 318 | { |
158 | jelle | 319 | T 58900 55650 5 10 1 1 0 6 1 |
123 | jelle | 320 | netname=RAM_DQM[2] |
120 | jelle | 321 | } |
158 | jelle | 322 | N 57400 55300 59000 55300 4 |
120 | jelle | 323 | { |
158 | jelle | 324 | T 58900 55350 5 10 1 1 0 6 1 |
123 | jelle | 325 | netname=RAM_DQM[3] |
120 | jelle | 326 | } |
158 | jelle | 327 | N 57400 56200 59000 56200 4 |
120 | jelle | 328 | { |
158 | jelle | 329 | T 58900 56250 5 10 1 1 0 6 1 |
120 | jelle | 330 | netname=RAM_CKE |
331 | } |
||
158 | jelle | 332 | N 57400 56500 59000 56500 4 |
120 | jelle | 333 | { |
158 | jelle | 334 | T 58900 56550 5 10 1 1 0 6 1 |
120 | jelle | 335 | netname=RAM_CLK |
336 | } |
||
158 | jelle | 337 | N 57400 54700 59000 54700 4 |
120 | jelle | 338 | { |
158 | jelle | 339 | T 58900 54750 5 10 1 1 0 6 1 |
120 | jelle | 340 | netname=RAM_CAS_N |
341 | } |
||
158 | jelle | 342 | N 57400 54400 59000 54400 4 |
120 | jelle | 343 | { |
158 | jelle | 344 | T 58900 54450 5 10 1 1 0 6 1 |
120 | jelle | 345 | netname=RAM_RAS_N |
346 | } |
||
158 | jelle | 347 | N 57400 53800 59000 53800 4 |
120 | jelle | 348 | { |
158 | jelle | 349 | T 58900 53850 5 10 1 1 0 6 1 |
120 | jelle | 350 | netname=RAM_WR_N |
351 | } |
||
158 | jelle | 352 | N 57400 53500 59000 53500 4 |
120 | jelle | 353 | { |
158 | jelle | 354 | T 58900 53550 5 10 1 1 0 6 1 |
120 | jelle | 355 | netname=RAM_CS_N |
356 | } |
||
158 | jelle | 357 | N 44100 50500 45800 50500 4 |
120 | jelle | 358 | { |
158 | jelle | 359 | T 45400 50550 5 10 1 1 0 6 1 |
120 | jelle | 360 | netname=RAM_A[00] |
361 | } |
||
158 | jelle | 362 | N 44100 50200 45800 50200 4 |
120 | jelle | 363 | { |
158 | jelle | 364 | T 45400 50250 5 10 1 1 0 6 1 |
120 | jelle | 365 | netname=RAM_A[01] |
366 | } |
||
158 | jelle | 367 | N 44100 49900 45800 49900 4 |
120 | jelle | 368 | { |
158 | jelle | 369 | T 45400 49950 5 10 1 1 0 6 1 |
120 | jelle | 370 | netname=RAM_A[02] |
371 | } |
||
158 | jelle | 372 | N 44100 49600 45800 49600 4 |
120 | jelle | 373 | { |
158 | jelle | 374 | T 45400 49650 5 10 1 1 0 6 1 |
120 | jelle | 375 | netname=RAM_A[03] |
376 | } |
||
158 | jelle | 377 | N 44100 49300 45800 49300 4 |
120 | jelle | 378 | { |
158 | jelle | 379 | T 45400 49350 5 10 1 1 0 6 1 |
120 | jelle | 380 | netname=RAM_A[04] |
381 | } |
||
158 | jelle | 382 | N 44100 49000 45800 49000 4 |
120 | jelle | 383 | { |
158 | jelle | 384 | T 45400 49050 5 10 1 1 0 6 1 |
120 | jelle | 385 | netname=RAM_A[05] |
386 | } |
||
158 | jelle | 387 | N 44100 48700 45800 48700 4 |
120 | jelle | 388 | { |
158 | jelle | 389 | T 45400 48750 5 10 1 1 0 6 1 |
120 | jelle | 390 | netname=RAM_A[06] |
391 | } |
||
158 | jelle | 392 | N 44100 48400 45800 48400 4 |
120 | jelle | 393 | { |
158 | jelle | 394 | T 45400 48450 5 10 1 1 0 6 1 |
120 | jelle | 395 | netname=RAM_A[07] |
396 | } |
||
158 | jelle | 397 | N 44100 48100 45800 48100 4 |
120 | jelle | 398 | { |
158 | jelle | 399 | T 45400 48150 5 10 1 1 0 6 1 |
120 | jelle | 400 | netname=RAM_A[08] |
401 | } |
||
158 | jelle | 402 | N 44100 47800 45800 47800 4 |
120 | jelle | 403 | { |
158 | jelle | 404 | T 45400 47850 5 10 1 1 0 6 1 |
120 | jelle | 405 | netname=RAM_A[09] |
406 | } |
||
158 | jelle | 407 | N 44100 47500 45800 47500 4 |
120 | jelle | 408 | { |
158 | jelle | 409 | T 45400 47550 5 10 1 1 0 6 1 |
120 | jelle | 410 | netname=RAM_A[10] |
411 | } |
||
158 | jelle | 412 | N 44100 47200 45800 47200 4 |
120 | jelle | 413 | { |
158 | jelle | 414 | T 45400 47250 5 10 1 1 0 6 1 |
120 | jelle | 415 | netname=RAM_A[11] |
416 | } |
||
158 | jelle | 417 | N 44100 46900 45800 46900 4 |
120 | jelle | 418 | { |
158 | jelle | 419 | T 45400 46950 5 10 1 1 0 6 1 |
120 | jelle | 420 | netname=RAM_A[12] |
421 | } |
||
158 | jelle | 422 | N 44100 46600 45800 46600 4 |
120 | jelle | 423 | { |
158 | jelle | 424 | T 45400 46650 5 10 1 1 0 6 1 |
120 | jelle | 425 | netname=RAM_A[13] |
426 | } |
||
158 | jelle | 427 | N 44100 46300 45800 46300 4 |
120 | jelle | 428 | { |
158 | jelle | 429 | T 45400 46350 5 10 1 1 0 6 1 |
120 | jelle | 430 | netname=RAM_A[14] |
431 | } |
||
158 | jelle | 432 | N 44100 45700 45800 45700 4 |
120 | jelle | 433 | { |
158 | jelle | 434 | T 45400 45750 5 10 1 1 0 6 1 |
120 | jelle | 435 | netname=RAM_DQM[0] |
436 | } |
||
158 | jelle | 437 | N 44100 45400 45800 45400 4 |
120 | jelle | 438 | { |
158 | jelle | 439 | T 45400 45450 5 10 1 1 0 6 1 |
120 | jelle | 440 | netname=RAM_DQM[1] |
441 | } |
||
158 | jelle | 442 | N 44100 44200 45800 44200 4 |
120 | jelle | 443 | { |
158 | jelle | 444 | T 45400 44250 5 10 1 1 0 6 1 |
120 | jelle | 445 | netname=RAM_CAS_N |
446 | } |
||
158 | jelle | 447 | N 44100 43900 45800 43900 4 |
120 | jelle | 448 | { |
158 | jelle | 449 | T 45400 43950 5 10 1 1 0 6 1 |
120 | jelle | 450 | netname=RAM_RAS_N |
451 | } |
||
158 | jelle | 452 | N 44100 42100 45800 42100 4 |
120 | jelle | 453 | { |
158 | jelle | 454 | T 45400 42150 5 10 1 1 0 6 1 |
120 | jelle | 455 | netname=RAM_WR_N |
456 | } |
||
158 | jelle | 457 | N 44100 41800 45800 41800 4 |
120 | jelle | 458 | { |
158 | jelle | 459 | T 45400 41850 5 10 1 1 0 6 1 |
120 | jelle | 460 | netname=RAM_CS_N |
461 | } |
||
158 | jelle | 462 | N 44100 42700 45800 42700 4 |
120 | jelle | 463 | { |
158 | jelle | 464 | T 45400 42750 5 10 1 1 0 6 1 |
120 | jelle | 465 | netname=RAM_CKE |
466 | } |
||
158 | jelle | 467 | N 44100 43000 45800 43000 4 |
120 | jelle | 468 | { |
158 | jelle | 469 | T 45400 43050 5 10 1 1 0 6 1 |
120 | jelle | 470 | netname=RAM_CLK |
471 | } |
||
158 | jelle | 472 | N 50600 50500 52000 50500 4 |
120 | jelle | 473 | { |
158 | jelle | 474 | T 50900 50550 5 10 1 1 0 0 1 |
120 | jelle | 475 | netname=RAM_D[00] |
476 | } |
||
158 | jelle | 477 | N 50600 50200 52000 50200 4 |
120 | jelle | 478 | { |
158 | jelle | 479 | T 50900 50250 5 10 1 1 0 0 1 |
120 | jelle | 480 | netname=RAM_D[01] |
481 | } |
||
158 | jelle | 482 | N 50600 49900 52000 49900 4 |
120 | jelle | 483 | { |
158 | jelle | 484 | T 50900 49950 5 10 1 1 0 0 1 |
120 | jelle | 485 | netname=RAM_D[02] |
486 | } |
||
158 | jelle | 487 | N 50600 49600 52000 49600 4 |
120 | jelle | 488 | { |
158 | jelle | 489 | T 50900 49650 5 10 1 1 0 0 1 |
120 | jelle | 490 | netname=RAM_D[03] |
491 | } |
||
158 | jelle | 492 | N 50600 49300 52000 49300 4 |
120 | jelle | 493 | { |
158 | jelle | 494 | T 50900 49350 5 10 1 1 0 0 1 |
120 | jelle | 495 | netname=RAM_D[04] |
496 | } |
||
158 | jelle | 497 | N 50600 49000 52000 49000 4 |
120 | jelle | 498 | { |
158 | jelle | 499 | T 50900 49050 5 10 1 1 0 0 1 |
120 | jelle | 500 | netname=RAM_D[05] |
501 | } |
||
158 | jelle | 502 | N 50600 48700 52000 48700 4 |
120 | jelle | 503 | { |
158 | jelle | 504 | T 50900 48750 5 10 1 1 0 0 1 |
120 | jelle | 505 | netname=RAM_D[06] |
506 | } |
||
158 | jelle | 507 | N 50600 48400 52000 48400 4 |
120 | jelle | 508 | { |
158 | jelle | 509 | T 50900 48450 5 10 1 1 0 0 1 |
120 | jelle | 510 | netname=RAM_D[07] |
511 | } |
||
158 | jelle | 512 | N 50600 48100 52000 48100 4 |
120 | jelle | 513 | { |
158 | jelle | 514 | T 50900 48150 5 10 1 1 0 0 1 |
120 | jelle | 515 | netname=RAM_D[08] |
516 | } |
||
158 | jelle | 517 | N 50600 47800 52000 47800 4 |
120 | jelle | 518 | { |
158 | jelle | 519 | T 50900 47850 5 10 1 1 0 0 1 |
120 | jelle | 520 | netname=RAM_D[09] |
521 | } |
||
158 | jelle | 522 | N 50600 47500 52000 47500 4 |
120 | jelle | 523 | { |
158 | jelle | 524 | T 50900 47550 5 10 1 1 0 0 1 |
120 | jelle | 525 | netname=RAM_D[10] |
526 | } |
||
158 | jelle | 527 | N 50600 47200 52000 47200 4 |
120 | jelle | 528 | { |
158 | jelle | 529 | T 50900 47250 5 10 1 1 0 0 1 |
120 | jelle | 530 | netname=RAM_D[11] |
531 | } |
||
158 | jelle | 532 | N 50600 46900 52000 46900 4 |
120 | jelle | 533 | { |
158 | jelle | 534 | T 50900 46950 5 10 1 1 0 0 1 |
120 | jelle | 535 | netname=RAM_D[12] |
536 | } |
||
158 | jelle | 537 | N 50600 46600 52000 46600 4 |
120 | jelle | 538 | { |
158 | jelle | 539 | T 50900 46650 5 10 1 1 0 0 1 |
120 | jelle | 540 | netname=RAM_D[13] |
541 | } |
||
158 | jelle | 542 | N 50600 46300 52000 46300 4 |
120 | jelle | 543 | { |
158 | jelle | 544 | T 50900 46350 5 10 1 1 0 0 1 |
120 | jelle | 545 | netname=RAM_D[14] |
546 | } |
||
158 | jelle | 547 | N 50600 46000 52000 46000 4 |
120 | jelle | 548 | { |
158 | jelle | 549 | T 50900 46050 5 10 1 1 0 0 1 |
120 | jelle | 550 | netname=RAM_D[15] |
551 | } |
||
158 | jelle | 552 | N 48900 54100 49200 54100 4 |
553 | N 49200 53800 48900 53800 4 |
||
554 | N 48900 53500 49200 53500 4 |
||
555 | N 48900 53200 49200 53200 4 |
||
556 | N 48900 52900 49200 52900 4 |
||
557 | N 48900 52600 49200 52600 4 |
||
558 | N 48900 52300 49200 52300 4 |
||
559 | C 49100 51800 1 0 0 gnd-1.sym |
||
560 | N 49200 52100 49200 54100 4 |
||
561 | C 50100 53500 1 90 0 capacitor-1.sym |
||
123 | jelle | 562 | { |
158 | jelle | 563 | T 49400 53700 5 10 0 0 90 0 1 |
267 | jelle | 564 | device=GRM21BR71H104KA01L |
158 | jelle | 565 | T 49600 53700 5 10 1 1 90 0 1 |
123 | jelle | 566 | refdes=C401 |
158 | jelle | 567 | T 49200 53700 5 10 0 0 90 0 1 |
123 | jelle | 568 | symversion=0.1 |
158 | jelle | 569 | T 50100 53500 5 10 0 0 90 0 1 |
123 | jelle | 570 | footprint=0805 |
158 | jelle | 571 | T 50200 53700 5 10 1 1 90 2 1 |
123 | jelle | 572 | value=100nF |
573 | } |
||
158 | jelle | 574 | C 51100 53500 1 90 0 capacitor-1.sym |
123 | jelle | 575 | { |
158 | jelle | 576 | T 50400 53700 5 10 0 0 90 0 1 |
267 | jelle | 577 | device=GRM21BR71H104KA01L |
158 | jelle | 578 | T 50600 53700 5 10 1 1 90 0 1 |
123 | jelle | 579 | refdes=C402 |
158 | jelle | 580 | T 50200 53700 5 10 0 0 90 0 1 |
123 | jelle | 581 | symversion=0.1 |
158 | jelle | 582 | T 51100 53500 5 10 0 0 90 0 1 |
123 | jelle | 583 | footprint=0805 |
158 | jelle | 584 | T 51200 53700 5 10 1 1 90 2 1 |
123 | jelle | 585 | value=100nF |
586 | } |
||
158 | jelle | 587 | C 52100 53500 1 90 0 capacitor-1.sym |
123 | jelle | 588 | { |
158 | jelle | 589 | T 51400 53700 5 10 0 0 90 0 1 |
267 | jelle | 590 | device=GRM21BR71H104KA01L |
158 | jelle | 591 | T 51600 53700 5 10 1 1 90 0 1 |
123 | jelle | 592 | refdes=C403 |
158 | jelle | 593 | T 51200 53700 5 10 0 0 90 0 1 |
123 | jelle | 594 | symversion=0.1 |
158 | jelle | 595 | T 52100 53500 5 10 0 0 90 0 1 |
123 | jelle | 596 | footprint=0805 |
158 | jelle | 597 | T 52200 53700 5 10 1 1 90 2 1 |
123 | jelle | 598 | value=100nF |
599 | } |
||
158 | jelle | 600 | C 53100 53500 1 90 0 capacitor-1.sym |
123 | jelle | 601 | { |
158 | jelle | 602 | T 52400 53700 5 10 0 0 90 0 1 |
267 | jelle | 603 | device=GRM21BR71H104KA01L |
158 | jelle | 604 | T 52600 53700 5 10 1 1 90 0 1 |
123 | jelle | 605 | refdes=C404 |
158 | jelle | 606 | T 52200 53700 5 10 0 0 90 0 1 |
123 | jelle | 607 | symversion=0.1 |
158 | jelle | 608 | T 53100 53500 5 10 0 0 90 0 1 |
123 | jelle | 609 | footprint=0805 |
158 | jelle | 610 | T 53200 53700 5 10 1 1 90 2 1 |
123 | jelle | 611 | value=100nF |
612 | } |
||
158 | jelle | 613 | N 48900 56500 49900 56500 4 |
614 | N 48900 56200 50900 56200 4 |
||
615 | N 50900 56200 50900 54400 4 |
||
616 | N 48900 55900 51900 55900 4 |
||
617 | N 51900 55900 51900 54400 4 |
||
618 | N 48900 55600 52900 55600 4 |
||
619 | N 52900 55600 52900 54400 4 |
||
620 | C 54100 53500 1 90 0 capacitor-1.sym |
||
123 | jelle | 621 | { |
158 | jelle | 622 | T 53400 53700 5 10 0 0 90 0 1 |
267 | jelle | 623 | device=GRM21BR71H104KA01L |
158 | jelle | 624 | T 53600 53700 5 10 1 1 90 0 1 |
123 | jelle | 625 | refdes=C405 |
158 | jelle | 626 | T 53200 53700 5 10 0 0 90 0 1 |
123 | jelle | 627 | symversion=0.1 |
158 | jelle | 628 | T 54100 53500 5 10 0 0 90 0 1 |
123 | jelle | 629 | footprint=0805 |
158 | jelle | 630 | T 54200 53700 5 10 1 1 90 2 1 |
123 | jelle | 631 | value=100nF |
632 | } |
||
158 | jelle | 633 | N 48900 55300 53900 55300 4 |
634 | N 53900 55300 53900 54400 4 |
||
635 | C 55100 53500 1 90 0 capacitor-1.sym |
||
123 | jelle | 636 | { |
158 | jelle | 637 | T 54400 53700 5 10 0 0 90 0 1 |
267 | jelle | 638 | device=GRM21BR71H104KA01L |
158 | jelle | 639 | T 54600 53700 5 10 1 1 90 0 1 |
123 | jelle | 640 | refdes=C406 |
158 | jelle | 641 | T 54200 53700 5 10 0 0 90 0 1 |
123 | jelle | 642 | symversion=0.1 |
158 | jelle | 643 | T 55100 53500 5 10 0 0 90 0 1 |
123 | jelle | 644 | footprint=0805 |
158 | jelle | 645 | T 55200 53700 5 10 1 1 90 2 1 |
123 | jelle | 646 | value=100nF |
647 | } |
||
158 | jelle | 648 | C 56100 53500 1 90 0 capacitor-1.sym |
123 | jelle | 649 | { |
158 | jelle | 650 | T 55400 53700 5 10 0 0 90 0 1 |
267 | jelle | 651 | device=GRM21BR71H104KA01L |
158 | jelle | 652 | T 55600 53700 5 10 1 1 90 0 1 |
123 | jelle | 653 | refdes=C407 |
158 | jelle | 654 | T 55200 53700 5 10 0 0 90 0 1 |
123 | jelle | 655 | symversion=0.1 |
158 | jelle | 656 | T 56100 53500 5 10 0 0 90 0 1 |
123 | jelle | 657 | footprint=0805 |
158 | jelle | 658 | T 56200 53700 5 10 1 1 90 2 1 |
123 | jelle | 659 | value=100nF |
660 | } |
||
158 | jelle | 661 | N 48900 55000 54900 55000 4 |
662 | N 54900 55000 54900 54400 4 |
||
663 | N 48900 54700 55900 54700 4 |
||
664 | N 55900 54700 55900 54400 4 |
||
665 | C 49800 53000 1 0 0 gnd-1.sym |
||
666 | N 49900 53500 49900 53300 4 |
||
667 | N 50900 53500 50900 53300 4 |
||
668 | C 50800 53000 1 0 0 gnd-1.sym |
||
669 | N 51900 53500 51900 53300 4 |
||
670 | C 51800 53000 1 0 0 gnd-1.sym |
||
671 | N 52900 53500 52900 53300 4 |
||
672 | C 52800 53000 1 0 0 gnd-1.sym |
||
673 | N 53900 53500 53900 53300 4 |
||
674 | C 53800 53000 1 0 0 gnd-1.sym |
||
675 | N 54900 53500 54900 53300 4 |
||
676 | C 54800 53000 1 0 0 gnd-1.sym |
||
677 | N 55900 53500 55900 53300 4 |
||
678 | C 55800 53000 1 0 0 gnd-1.sym |
||
679 | C 49700 56500 1 0 0 generic-power.sym |
||
123 | jelle | 680 | { |
158 | jelle | 681 | T 49900 56750 5 10 1 1 0 3 1 |
123 | jelle | 682 | net=+3.125V:1 |
683 | } |
||
158 | jelle | 684 | N 49900 56200 49900 56500 4 |
685 | N 49900 56200 49900 55900 4 |
||
686 | N 49900 55900 49900 55600 4 |
||
687 | N 49900 55600 49900 55300 4 |
||
688 | N 49900 55300 49900 55000 4 |
||
689 | N 49900 55000 49900 54700 4 |
||
690 | N 49900 54700 49900 54400 4 |
||
691 | N 48900 61600 50225 61600 4 |
||
123 | jelle | 692 | { |
158 | jelle | 693 | T 49000 61650 5 10 1 1 0 0 1 |
123 | jelle | 694 | netname=RAM_D[00] |
695 | } |
||
158 | jelle | 696 | N 48900 61300 50225 61300 4 |
123 | jelle | 697 | { |
158 | jelle | 698 | T 49000 61350 5 10 1 1 0 0 1 |
123 | jelle | 699 | netname=RAM_D[01] |
700 | } |
||
158 | jelle | 701 | N 48900 61000 50225 61000 4 |
123 | jelle | 702 | { |
158 | jelle | 703 | T 49000 61050 5 10 1 1 0 0 1 |
123 | jelle | 704 | netname=RAM_D[02] |
705 | } |
||
158 | jelle | 706 | N 48900 60700 50225 60700 4 |
123 | jelle | 707 | { |
158 | jelle | 708 | T 49000 60750 5 10 1 1 0 0 1 |
123 | jelle | 709 | netname=RAM_D[03] |
710 | } |
||
158 | jelle | 711 | N 48900 60400 50225 60400 4 |
123 | jelle | 712 | { |
158 | jelle | 713 | T 49000 60450 5 10 1 1 0 0 1 |
123 | jelle | 714 | netname=RAM_D[04] |
715 | } |
||
158 | jelle | 716 | N 48900 60100 50225 60100 4 |
123 | jelle | 717 | { |
158 | jelle | 718 | T 49000 60150 5 10 1 1 0 0 1 |
123 | jelle | 719 | netname=RAM_D[05] |
720 | } |
||
158 | jelle | 721 | N 48900 59800 50225 59800 4 |
123 | jelle | 722 | { |
158 | jelle | 723 | T 49000 59850 5 10 1 1 0 0 1 |
123 | jelle | 724 | netname=RAM_D[06] |
725 | } |
||
158 | jelle | 726 | N 48900 59500 50225 59500 4 |
123 | jelle | 727 | { |
158 | jelle | 728 | T 49000 59550 5 10 1 1 0 0 1 |
123 | jelle | 729 | netname=RAM_D[07] |
730 | } |
||
158 | jelle | 731 | N 48900 59200 50225 59200 4 |
123 | jelle | 732 | { |
158 | jelle | 733 | T 49000 59250 5 10 1 1 0 0 1 |
123 | jelle | 734 | netname=RAM_D[08] |
735 | } |
||
158 | jelle | 736 | N 48900 58900 50225 58900 4 |
123 | jelle | 737 | { |
158 | jelle | 738 | T 49000 58950 5 10 1 1 0 0 1 |
123 | jelle | 739 | netname=RAM_D[09] |
740 | } |
||
158 | jelle | 741 | N 48900 58600 50225 58600 4 |
123 | jelle | 742 | { |
158 | jelle | 743 | T 49000 58650 5 10 1 1 0 0 1 |
123 | jelle | 744 | netname=RAM_D[10] |
745 | } |
||
158 | jelle | 746 | N 48900 58300 50225 58300 4 |
123 | jelle | 747 | { |
158 | jelle | 748 | T 49000 58350 5 10 1 1 0 0 1 |
123 | jelle | 749 | netname=RAM_D[11] |
750 | } |
||
158 | jelle | 751 | N 48900 58000 50225 58000 4 |
123 | jelle | 752 | { |
158 | jelle | 753 | T 49000 58050 5 10 1 1 0 0 1 |
123 | jelle | 754 | netname=RAM_D[12] |
755 | } |
||
158 | jelle | 756 | N 48900 57700 50225 57700 4 |
123 | jelle | 757 | { |
158 | jelle | 758 | T 49000 57750 5 10 1 1 0 0 1 |
123 | jelle | 759 | netname=RAM_D[13] |
760 | } |
||
158 | jelle | 761 | N 48900 57400 50225 57400 4 |
123 | jelle | 762 | { |
158 | jelle | 763 | T 49000 57450 5 10 1 1 0 0 1 |
123 | jelle | 764 | netname=RAM_D[14] |
765 | } |
||
158 | jelle | 766 | N 48900 57100 50225 57100 4 |
123 | jelle | 767 | { |
158 | jelle | 768 | T 49000 57150 5 10 1 1 0 0 1 |
123 | jelle | 769 | netname=RAM_D[15] |
770 | } |
||
158 | jelle | 771 | N 46000 61600 44600 61600 4 |
123 | jelle | 772 | { |
158 | jelle | 773 | T 45900 61650 5 10 1 1 0 6 1 |
123 | jelle | 774 | netname=RAM_A[00] |
775 | } |
||
158 | jelle | 776 | N 46000 61300 44600 61300 4 |
123 | jelle | 777 | { |
158 | jelle | 778 | T 45900 61350 5 10 1 1 0 6 1 |
123 | jelle | 779 | netname=RAM_A[01] |
780 | } |
||
158 | jelle | 781 | N 46000 61000 44600 61000 4 |
123 | jelle | 782 | { |
158 | jelle | 783 | T 45900 61050 5 10 1 1 0 6 1 |
123 | jelle | 784 | netname=RAM_A[02] |
785 | } |
||
158 | jelle | 786 | N 46000 60700 44600 60700 4 |
123 | jelle | 787 | { |
158 | jelle | 788 | T 45900 60750 5 10 1 1 0 6 1 |
123 | jelle | 789 | netname=RAM_A[03] |
790 | } |
||
158 | jelle | 791 | N 46000 60400 44600 60400 4 |
123 | jelle | 792 | { |
158 | jelle | 793 | T 45900 60450 5 10 1 1 0 6 1 |
123 | jelle | 794 | netname=RAM_A[04] |
795 | } |
||
158 | jelle | 796 | N 46000 60100 44600 60100 4 |
123 | jelle | 797 | { |
158 | jelle | 798 | T 45900 60150 5 10 1 1 0 6 1 |
123 | jelle | 799 | netname=RAM_A[05] |
800 | } |
||
158 | jelle | 801 | N 46000 59800 44600 59800 4 |
123 | jelle | 802 | { |
158 | jelle | 803 | T 45900 59850 5 10 1 1 0 6 1 |
123 | jelle | 804 | netname=RAM_A[06] |
805 | } |
||
158 | jelle | 806 | N 46000 59500 44600 59500 4 |
123 | jelle | 807 | { |
158 | jelle | 808 | T 45900 59550 5 10 1 1 0 6 1 |
123 | jelle | 809 | netname=RAM_A[07] |
810 | } |
||
158 | jelle | 811 | N 46000 59200 44600 59200 4 |
123 | jelle | 812 | { |
158 | jelle | 813 | T 45900 59250 5 10 1 1 0 6 1 |
123 | jelle | 814 | netname=RAM_A[08] |
815 | } |
||
158 | jelle | 816 | N 46000 58900 44600 58900 4 |
123 | jelle | 817 | { |
158 | jelle | 818 | T 45900 58950 5 10 1 1 0 6 1 |
123 | jelle | 819 | netname=RAM_A[09] |
820 | } |
||
158 | jelle | 821 | N 46000 58600 44600 58600 4 |
123 | jelle | 822 | { |
158 | jelle | 823 | T 45900 58650 5 10 1 1 0 6 1 |
123 | jelle | 824 | netname=RAM_A[10] |
825 | } |
||
158 | jelle | 826 | N 46000 58300 44600 58300 4 |
123 | jelle | 827 | { |
158 | jelle | 828 | T 45900 58350 5 10 1 1 0 6 1 |
123 | jelle | 829 | netname=RAM_A[11] |
830 | } |
||
158 | jelle | 831 | N 46000 58000 44600 58000 4 |
123 | jelle | 832 | { |
158 | jelle | 833 | T 45900 58050 5 10 1 1 0 6 1 |
123 | jelle | 834 | netname=RAM_A[12] |
835 | } |
||
158 | jelle | 836 | N 46000 57400 44600 57400 4 |
123 | jelle | 837 | { |
158 | jelle | 838 | T 45900 57450 5 10 1 1 0 6 1 |
123 | jelle | 839 | netname=RAM_A[13] |
840 | } |
||
158 | jelle | 841 | N 46000 57100 44600 57100 4 |
123 | jelle | 842 | { |
158 | jelle | 843 | T 45900 57150 5 10 1 1 0 6 1 |
123 | jelle | 844 | netname=RAM_A[14] |
845 | } |
||
158 | jelle | 846 | N 44400 55600 46000 55600 4 |
123 | jelle | 847 | { |
158 | jelle | 848 | T 45900 55650 5 10 1 1 0 6 1 |
123 | jelle | 849 | netname=RAM_DQM[0] |
850 | } |
||
158 | jelle | 851 | N 44400 55300 46000 55300 4 |
123 | jelle | 852 | { |
158 | jelle | 853 | T 45900 55350 5 10 1 1 0 6 1 |
123 | jelle | 854 | netname=RAM_DQM[1] |
855 | } |
||
158 | jelle | 856 | N 44400 56200 46000 56200 4 |
123 | jelle | 857 | { |
158 | jelle | 858 | T 45900 56250 5 10 1 1 0 6 1 |
123 | jelle | 859 | netname=RAM_CKE |
860 | } |
||
158 | jelle | 861 | N 44400 56500 46000 56500 4 |
123 | jelle | 862 | { |
158 | jelle | 863 | T 45900 56550 5 10 1 1 0 6 1 |
123 | jelle | 864 | netname=RAM_CLK |
865 | } |
||
158 | jelle | 866 | N 44400 54700 46000 54700 4 |
123 | jelle | 867 | { |
158 | jelle | 868 | T 45900 54750 5 10 1 1 0 6 1 |
123 | jelle | 869 | netname=RAM_CAS_N |
870 | } |
||
158 | jelle | 871 | N 44400 54400 46000 54400 4 |
123 | jelle | 872 | { |
158 | jelle | 873 | T 45900 54450 5 10 1 1 0 6 1 |
123 | jelle | 874 | netname=RAM_RAS_N |
875 | } |
||
158 | jelle | 876 | N 44400 53800 46000 53800 4 |
123 | jelle | 877 | { |
158 | jelle | 878 | T 45900 53850 5 10 1 1 0 6 1 |
123 | jelle | 879 | netname=RAM_WR_N |
880 | } |
||
158 | jelle | 881 | N 44400 53500 46000 53500 4 |
123 | jelle | 882 | { |
158 | jelle | 883 | T 45900 53550 5 10 1 1 0 6 1 |
123 | jelle | 884 | netname=RAM_CS_N |
885 | } |
||
158 | jelle | 886 | N 44100 45100 45800 45100 4 |
123 | jelle | 887 | { |
158 | jelle | 888 | T 45400 45150 5 10 1 1 0 6 1 |
123 | jelle | 889 | netname=RAM_DQM[2] |
890 | } |
||
158 | jelle | 891 | N 44100 44800 45800 44800 4 |
123 | jelle | 892 | { |
158 | jelle | 893 | T 45400 44850 5 10 1 1 0 6 1 |
123 | jelle | 894 | netname=RAM_DQM[3] |
895 | } |
||
158 | jelle | 896 | N 50600 45700 52000 45700 4 |
123 | jelle | 897 | { |
158 | jelle | 898 | T 50900 45750 5 10 1 1 0 0 1 |
123 | jelle | 899 | netname=RAM_D[16] |
900 | } |
||
158 | jelle | 901 | N 50600 45400 52000 45400 4 |
123 | jelle | 902 | { |
158 | jelle | 903 | T 50900 45450 5 10 1 1 0 0 1 |
123 | jelle | 904 | netname=RAM_D[17] |
905 | } |
||
158 | jelle | 906 | N 50600 45100 52000 45100 4 |
123 | jelle | 907 | { |
158 | jelle | 908 | T 50900 45150 5 10 1 1 0 0 1 |
123 | jelle | 909 | netname=RAM_D[18] |
910 | } |
||
158 | jelle | 911 | N 50600 44800 52000 44800 4 |
123 | jelle | 912 | { |
158 | jelle | 913 | T 50900 44850 5 10 1 1 0 0 1 |
123 | jelle | 914 | netname=RAM_D[19] |
915 | } |
||
158 | jelle | 916 | N 50600 44500 52000 44500 4 |
123 | jelle | 917 | { |
158 | jelle | 918 | T 50900 44550 5 10 1 1 0 0 1 |
123 | jelle | 919 | netname=RAM_D[20] |
920 | } |
||
158 | jelle | 921 | N 50600 44200 52000 44200 4 |
123 | jelle | 922 | { |
158 | jelle | 923 | T 50900 44250 5 10 1 1 0 0 1 |
123 | jelle | 924 | netname=RAM_D[21] |
925 | } |
||
158 | jelle | 926 | N 50600 43900 52000 43900 4 |
123 | jelle | 927 | { |
158 | jelle | 928 | T 50900 43950 5 10 1 1 0 0 1 |
123 | jelle | 929 | netname=RAM_D[22] |
930 | } |
||
158 | jelle | 931 | N 50600 43600 52000 43600 4 |
123 | jelle | 932 | { |
158 | jelle | 933 | T 50900 43650 5 10 1 1 0 0 1 |
123 | jelle | 934 | netname=RAM_D[23] |
935 | } |
||
158 | jelle | 936 | N 50600 43300 52000 43300 4 |
123 | jelle | 937 | { |
158 | jelle | 938 | T 50900 43350 5 10 1 1 0 0 1 |
123 | jelle | 939 | netname=RAM_D[24] |
940 | } |
||
158 | jelle | 941 | N 50600 43000 52000 43000 4 |
123 | jelle | 942 | { |
158 | jelle | 943 | T 50900 43050 5 10 1 1 0 0 1 |
123 | jelle | 944 | netname=RAM_D[25] |
945 | } |
||
158 | jelle | 946 | N 50600 42700 52000 42700 4 |
123 | jelle | 947 | { |
158 | jelle | 948 | T 50900 42750 5 10 1 1 0 0 1 |
123 | jelle | 949 | netname=RAM_D[26] |
950 | } |
||
158 | jelle | 951 | N 50600 42400 52000 42400 4 |
123 | jelle | 952 | { |
158 | jelle | 953 | T 50900 42450 5 10 1 1 0 0 1 |
123 | jelle | 954 | netname=RAM_D[27] |
955 | } |
||
158 | jelle | 956 | N 50600 42100 52000 42100 4 |
123 | jelle | 957 | { |
158 | jelle | 958 | T 50900 42150 5 10 1 1 0 0 1 |
123 | jelle | 959 | netname=RAM_D[28] |
960 | } |
||
158 | jelle | 961 | N 50600 41800 52000 41800 4 |
123 | jelle | 962 | { |
158 | jelle | 963 | T 50900 41850 5 10 1 1 0 0 1 |
123 | jelle | 964 | netname=RAM_D[29] |
965 | } |
||
158 | jelle | 966 | N 50600 41500 52000 41500 4 |
123 | jelle | 967 | { |
158 | jelle | 968 | T 50900 41550 5 10 1 1 0 0 1 |
123 | jelle | 969 | netname=RAM_D[30] |
970 | } |
||
158 | jelle | 971 | N 50600 41200 52000 41200 4 |
123 | jelle | 972 | { |
158 | jelle | 973 | T 50900 41250 5 10 1 1 0 0 1 |
123 | jelle | 974 | netname=RAM_D[31] |
975 | } |
||
158 | jelle | 976 | C 46000 51700 1 0 0 MT48LC16M16A2.sym |
123 | jelle | 977 | { |
158 | jelle | 978 | T 46300 62000 5 10 1 1 0 0 1 |
310 | jelle | 979 | device=MT48LC16M16A2P-7E:D |
158 | jelle | 980 | T 46300 62200 5 10 1 1 0 0 1 |
123 | jelle | 981 | footprint=TSOPII54 |
158 | jelle | 982 | T 46300 62400 5 10 1 1 0 0 1 |
983 | refdes=U401 |
||
310 | jelle | 984 | T 46000 51700 5 10 0 0 0 0 1 |
985 | description=dd |
||
158 | jelle | 986 | } |
987 | C 59000 51700 1 0 0 MT48LC16M16A2.sym |
||
988 | { |
||
989 | T 59300 62000 5 10 1 1 0 0 1 |
||
310 | jelle | 990 | device=MT48LC16M16A2P-7E:D |
158 | jelle | 991 | T 59300 62200 5 10 1 1 0 0 1 |
992 | footprint=TSOPII54 |
||
993 | T 59300 62400 5 10 1 1 0 0 1 |
||
123 | jelle | 994 | refdes=U403 |
995 | } |
||
158 | jelle | 996 | C 45800 40600 1 0 0 LPC3180-RAM.sym |
123 | jelle | 997 | { |
175 | jelle | 998 | T 50100 50900 5 10 1 1 0 6 1 |
158 | jelle | 999 | block=RAM |
175 | jelle | 1000 | T 46300 50900 5 10 1 1 0 0 1 |
158 | jelle | 1001 | device=LPC3180FEL320 |
175 | jelle | 1002 | T 46300 51100 5 10 1 1 0 0 1 |
158 | jelle | 1003 | footprint=SOT824 |
175 | jelle | 1004 | T 46300 51300 5 10 1 1 0 0 1 |
338 | jelle | 1005 | refdes=U001 |
123 | jelle | 1006 | } |
158 | jelle | 1007 | C 66300 44700 1 0 0 LPC3180-VDD-RAM.sym |
123 | jelle | 1008 | { |
158 | jelle | 1009 | T 69800 48100 5 10 1 1 0 6 1 |
1010 | block=VDD (RAM) |
||
1011 | T 66800 48100 5 10 1 1 0 0 1 |
||
1012 | device=LPC3180FEL320 |
||
1013 | T 66800 48300 5 10 1 1 0 0 1 |
||
123 | jelle | 1014 | footprint=SOT824 |
158 | jelle | 1015 | T 66800 48500 5 10 1 1 0 0 1 |
338 | jelle | 1016 | refdes=U001 |
158 | jelle | 1017 | } |
1018 | C 55600 44100 1 0 0 LPC3180-VSS-RAM.sym |
||
1019 | { |
||
1020 | T 59100 48100 5 10 1 1 0 6 1 |
||
1021 | block=VSS (RAM) |
||
1022 | T 56100 48100 5 10 1 1 0 0 1 |
||
123 | jelle | 1023 | device=LPC3180FEL320 |
158 | jelle | 1024 | T 56100 48300 5 10 1 1 0 0 1 |
1025 | footprint=SOT824 |
||
1026 | T 56100 48500 5 10 1 1 0 0 1 |
||
338 | jelle | 1027 | refdes=U001 |
123 | jelle | 1028 | } |
158 | jelle | 1029 | C 55100 44200 1 0 0 gnd-1.sym |
1030 | N 55600 47700 55200 47700 4 |
||
1031 | N 55200 47700 55200 44500 4 |
||
1032 | N 55600 44700 55200 44700 4 |
||
1033 | N 55600 45000 55200 45000 4 |
||
1034 | N 55600 45300 55200 45300 4 |
||
1035 | N 55600 45600 55200 45600 4 |
||
1036 | N 55600 45900 55200 45900 4 |
||
1037 | N 55600 46200 55200 46200 4 |
||
1038 | N 55600 46500 55200 46500 4 |
||
1039 | N 55600 46800 55200 46800 4 |
||
1040 | N 55600 47100 55200 47100 4 |
||
1041 | N 55600 47400 55200 47400 4 |
||
159 | jelle | 1042 | C 64900 46900 1 90 0 capacitor-1.sym |
158 | jelle | 1043 | { |
159 | jelle | 1044 | T 64200 47100 5 10 0 0 90 0 1 |
267 | jelle | 1045 | device=GRM21BR71H104KA01L |
159 | jelle | 1046 | T 64400 47100 5 10 1 1 90 0 1 |
158 | jelle | 1047 | refdes=C420 |
159 | jelle | 1048 | T 64000 47100 5 10 0 0 90 0 1 |
158 | jelle | 1049 | symversion=0.1 |
159 | jelle | 1050 | T 64900 46900 5 10 0 0 90 0 1 |
158 | jelle | 1051 | footprint=0805 |
159 | jelle | 1052 | T 65000 47100 5 10 1 1 90 2 1 |
158 | jelle | 1053 | value=100nF |
1054 | } |
||
159 | jelle | 1055 | C 63800 46900 1 90 0 capacitor-1.sym |
158 | jelle | 1056 | { |
159 | jelle | 1057 | T 63100 47100 5 10 0 0 90 0 1 |
267 | jelle | 1058 | device=GRM21BR71H104KA01L |
159 | jelle | 1059 | T 63300 47100 5 10 1 1 90 0 1 |
158 | jelle | 1060 | refdes=C418 |
159 | jelle | 1061 | T 62900 47100 5 10 0 0 90 0 1 |
158 | jelle | 1062 | symversion=0.1 |
159 | jelle | 1063 | T 63800 46900 5 10 0 0 90 0 1 |
158 | jelle | 1064 | footprint=0805 |
159 | jelle | 1065 | T 63900 47100 5 10 1 1 90 2 1 |
158 | jelle | 1066 | value=100nF |
1067 | } |
||
159 | jelle | 1068 | C 62700 46900 1 90 0 capacitor-1.sym |
158 | jelle | 1069 | { |
159 | jelle | 1070 | T 62000 47100 5 10 0 0 90 0 1 |
267 | jelle | 1071 | device=GRM21BR71H104KA01L |
159 | jelle | 1072 | T 62200 47100 5 10 1 1 90 0 1 |
158 | jelle | 1073 | refdes=C416 |
159 | jelle | 1074 | T 61800 47100 5 10 0 0 90 0 1 |
158 | jelle | 1075 | symversion=0.1 |
159 | jelle | 1076 | T 62700 46900 5 10 0 0 90 0 1 |
158 | jelle | 1077 | footprint=0805 |
159 | jelle | 1078 | T 62800 47100 5 10 1 1 90 2 1 |
158 | jelle | 1079 | value=100nF |
1080 | } |
||
159 | jelle | 1081 | C 61600 46900 1 90 0 capacitor-1.sym |
158 | jelle | 1082 | { |
159 | jelle | 1083 | T 60900 47100 5 10 0 0 90 0 1 |
267 | jelle | 1084 | device=GRM21BR71H104KA01L |
159 | jelle | 1085 | T 61100 47100 5 10 1 1 90 0 1 |
158 | jelle | 1086 | refdes=C414 |
159 | jelle | 1087 | T 60700 47100 5 10 0 0 90 0 1 |
158 | jelle | 1088 | symversion=0.1 |
159 | jelle | 1089 | T 61600 46900 5 10 0 0 90 0 1 |
158 | jelle | 1090 | footprint=0805 |
159 | jelle | 1091 | T 61700 47100 5 10 1 1 90 2 1 |
158 | jelle | 1092 | value=100nF |
1093 | } |
||
159 | jelle | 1094 | C 64900 43700 1 90 0 capacitor-1.sym |
158 | jelle | 1095 | { |
159 | jelle | 1096 | T 64200 43900 5 10 0 0 90 0 1 |
267 | jelle | 1097 | device=GRM21BR71H104KA01L |
159 | jelle | 1098 | T 64400 43900 5 10 1 1 90 0 1 |
158 | jelle | 1099 | refdes=C423 |
159 | jelle | 1100 | T 64000 43900 5 10 0 0 90 0 1 |
158 | jelle | 1101 | symversion=0.1 |
159 | jelle | 1102 | T 64900 43700 5 10 0 0 90 0 1 |
158 | jelle | 1103 | footprint=0805 |
159 | jelle | 1104 | T 65000 43900 5 10 1 1 90 2 1 |
158 | jelle | 1105 | value=100nF |
1106 | } |
||
159 | jelle | 1107 | C 63800 43700 1 90 0 capacitor-1.sym |
158 | jelle | 1108 | { |
159 | jelle | 1109 | T 63100 43900 5 10 0 0 90 0 1 |
267 | jelle | 1110 | device=GRM21BR71H104KA01L |
159 | jelle | 1111 | T 63300 43900 5 10 1 1 90 0 1 |
158 | jelle | 1112 | refdes=C422 |
159 | jelle | 1113 | T 62900 43900 5 10 0 0 90 0 1 |
158 | jelle | 1114 | symversion=0.1 |
159 | jelle | 1115 | T 63800 43700 5 10 0 0 90 0 1 |
158 | jelle | 1116 | footprint=0805 |
159 | jelle | 1117 | T 63900 43900 5 10 1 1 90 2 1 |
158 | jelle | 1118 | value=100nF |
1119 | } |
||
159 | jelle | 1120 | C 62700 43700 1 90 0 capacitor-1.sym |
158 | jelle | 1121 | { |
159 | jelle | 1122 | T 62000 43900 5 10 0 0 90 0 1 |
267 | jelle | 1123 | device=GRM21BR71H104KA01L |
159 | jelle | 1124 | T 62200 43900 5 10 1 1 90 0 1 |
158 | jelle | 1125 | refdes=C421 |
159 | jelle | 1126 | T 61800 43900 5 10 0 0 90 0 1 |
158 | jelle | 1127 | symversion=0.1 |
159 | jelle | 1128 | T 62700 43700 5 10 0 0 90 0 1 |
158 | jelle | 1129 | footprint=0805 |
159 | jelle | 1130 | T 62800 43900 5 10 1 1 90 2 1 |
158 | jelle | 1131 | value=100nF |
1132 | } |
||
159 | jelle | 1133 | C 61600 43700 1 90 0 capacitor-1.sym |
158 | jelle | 1134 | { |
159 | jelle | 1135 | T 60900 43900 5 10 0 0 90 0 1 |
267 | jelle | 1136 | device=GRM21BR71H104KA01L |
159 | jelle | 1137 | T 61100 43900 5 10 1 1 90 0 1 |
158 | jelle | 1138 | refdes=C419 |
159 | jelle | 1139 | T 60700 43900 5 10 0 0 90 0 1 |
158 | jelle | 1140 | symversion=0.1 |
159 | jelle | 1141 | T 61600 43700 5 10 0 0 90 0 1 |
158 | jelle | 1142 | footprint=0805 |
159 | jelle | 1143 | T 61700 43900 5 10 1 1 90 2 1 |
158 | jelle | 1144 | value=100nF |
1145 | } |
||
159 | jelle | 1146 | C 60500 43700 1 90 0 capacitor-1.sym |
158 | jelle | 1147 | { |
159 | jelle | 1148 | T 59800 43900 5 10 0 0 90 0 1 |
267 | jelle | 1149 | device=GRM21BR71H104KA01L |
159 | jelle | 1150 | T 60000 43900 5 10 1 1 90 0 1 |
158 | jelle | 1151 | refdes=C417 |
159 | jelle | 1152 | T 59600 43900 5 10 0 0 90 0 1 |
158 | jelle | 1153 | symversion=0.1 |
159 | jelle | 1154 | T 60500 43700 5 10 0 0 90 0 1 |
158 | jelle | 1155 | footprint=0805 |
159 | jelle | 1156 | T 60600 43900 5 10 1 1 90 2 1 |
158 | jelle | 1157 | value=100nF |
1158 | } |
||
159 | jelle | 1159 | C 61300 46400 1 0 0 gnd-1.sym |
1160 | N 61400 46900 61400 46700 4 |
||
1161 | C 62400 46400 1 0 0 gnd-1.sym |
||
1162 | N 62500 46900 62500 46700 4 |
||
1163 | C 63500 46400 1 0 0 gnd-1.sym |
||
1164 | N 63600 46900 63600 46700 4 |
||
1165 | C 64600 46400 1 0 0 gnd-1.sym |
||
1166 | N 64700 46900 64700 46700 4 |
||
1167 | C 64600 43200 1 0 0 gnd-1.sym |
||
1168 | N 64700 43700 64700 43500 4 |
||
1169 | C 63500 43200 1 0 0 gnd-1.sym |
||
1170 | N 63600 43700 63600 43500 4 |
||
1171 | C 62400 43200 1 0 0 gnd-1.sym |
||
1172 | N 62500 43700 62500 43500 4 |
||
1173 | C 61300 43200 1 0 0 gnd-1.sym |
||
1174 | N 61400 43700 61400 43500 4 |
||
1175 | C 60200 43200 1 0 0 gnd-1.sym |
||
1176 | N 60300 43700 60300 43500 4 |
||
1177 | N 63600 44600 63600 45000 4 |
||
1178 | N 61400 44600 61400 45400 4 |
||
1179 | N 60300 44600 60300 45600 4 |
||
1180 | N 62500 44600 62500 45200 4 |
||
1181 | N 64700 48000 65600 48000 4 |
||
1182 | N 63600 47800 63600 48200 4 |
||
1183 | N 62500 47800 62500 48400 4 |
||
1184 | N 61400 47800 61400 48600 4 |
||
1185 | N 61400 48600 66200 48600 4 |
||
158 | jelle | 1186 | N 66200 48600 66200 47700 4 |
159 | jelle | 1187 | N 62500 48400 66000 48400 4 |
158 | jelle | 1188 | N 66000 48400 66000 47400 4 |
159 | jelle | 1189 | N 63600 48200 65800 48200 4 |
158 | jelle | 1190 | N 65800 48200 65800 47100 4 |
1191 | N 65600 46800 65600 48000 4 |
||
159 | jelle | 1192 | N 65400 46500 65400 45600 4 |
1193 | N 60300 45600 65400 45600 4 |
||
1194 | N 65600 46200 65600 45400 4 |
||
1195 | N 61400 45400 65600 45400 4 |
||
1196 | N 62500 45200 65800 45200 4 |
||
1197 | N 66000 45600 66000 45000 4 |
||
1198 | N 63600 45000 66000 45000 4 |
||
1199 | N 65800 45900 65800 45200 4 |
||
1200 | N 66200 45300 66200 44800 4 |
||
1201 | N 64700 44800 66200 44800 4 |
||
158 | jelle | 1202 | N 66300 45300 66200 45300 4 |
1203 | N 66000 45600 66300 45600 4 |
||
1204 | N 65800 45900 66300 45900 4 |
||
1205 | N 65600 46200 66300 46200 4 |
||
1206 | N 65400 46500 66300 46500 4 |
||
1207 | N 65600 46800 66300 46800 4 |
||
1208 | N 65800 47100 66300 47100 4 |
||
1209 | N 66000 47400 66300 47400 4 |
||
1210 | N 66200 47700 66300 47700 4 |
||
159 | jelle | 1211 | C 64500 48800 1 0 0 generic-power.sym |
1212 | { |
||
1213 | T 64700 49050 5 10 1 1 0 3 1 |
||
1214 | net=+3.125V:1 |
||
1215 | } |
||
1216 | C 64500 45800 1 0 0 generic-power.sym |
||
1217 | { |
||
1218 | T 64700 46050 5 10 1 1 0 3 1 |
||
1219 | net=+3.125V:1 |
||
1220 | } |
||
1221 | N 64700 48800 64700 48600 4 |
||
1222 | N 64700 48600 64700 48400 4 |
||
1223 | N 64700 48400 64700 48200 4 |
||
1224 | N 64700 47800 64700 48200 4 |
||
1225 | N 64700 45800 64700 45600 4 |
||
1226 | N 64700 45600 64700 45400 4 |
||
1227 | N 64700 45400 64700 45200 4 |
||
1228 | N 64700 45200 64700 45000 4 |
||
1229 | N 64700 44600 64700 45000 4 |
||
219 | jelle | 1230 | N 44100 43300 45800 43300 4 |
1231 | { |
||
1232 | T 45400 43350 5 10 1 1 0 6 1 |
||
1233 | netname=RAM_CLKIN |
||
1234 | } |
||
1235 | N 54600 56800 56300 56800 4 |
||
1236 | { |
||
1237 | T 55900 56850 5 10 1 1 0 6 1 |
||
1238 | netname=RAM_CLKIN |
||
1239 | } |
||
1240 | C 56300 56700 1 0 0 resistor-2.sym |
||
1241 | { |
||
1242 | T 56700 57050 5 10 0 0 0 0 1 |
||
267 | jelle | 1243 | device=MC 0.1W 0805 0R |
219 | jelle | 1244 | T 56500 57000 5 10 1 1 0 0 1 |
1245 | refdes=R402 |
||
1246 | T 56500 56600 5 10 1 1 0 2 1 |
||
1247 | value=0 |
||
1248 | T 56300 56700 5 10 0 1 0 0 1 |
||
1249 | footprint=0805 |
||
1250 | } |
||
1251 | N 57200 56800 57700 56800 4 |
||
1252 | N 57700 56800 57700 56500 4 |
||
1253 | N 44700 56800 44700 56500 4 |
||
1254 | C 43300 56700 1 0 0 resistor-2.sym |
||
1255 | { |
||
1256 | T 43700 57050 5 10 0 0 0 0 1 |
||
267 | jelle | 1257 | device=MC 0.1W 0805 0R |
219 | jelle | 1258 | T 43500 57000 5 10 1 1 0 0 1 |
1259 | refdes=R401 |
||
1260 | T 43500 56600 5 10 1 1 0 2 1 |
||
1261 | value=0 |
||
1262 | T 43300 56700 5 10 0 1 0 0 1 |
||
1263 | footprint=0805 |
||
1264 | } |
||
1265 | N 41600 56800 43300 56800 4 |
||
1266 | { |
||
1267 | T 42900 56850 5 10 1 1 0 6 1 |
||
1268 | netname=RAM_CLKIN |
||
1269 | } |
||
1270 | N 44200 56800 44700 56800 4 |