Rev 138 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
138 | jelle | 1 | v 20060123 1 |
146 | jelle | 2 | B 500 300 3800 9900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
138 | jelle | 3 | T 4100 10300 9 10 0 0 0 0 1 |
4 | uselicense=unlimited |
||
5 | T 4100 10500 9 10 0 0 0 0 1 |
||
92 | jelle | 6 | distlicense=GPL (v2 or any later version) |
138 | jelle | 7 | T 4100 10700 9 10 0 0 0 0 1 |
8 | copyright=2008 Tibor Palinkas |
||
9 | T 4100 10900 9 10 0 0 0 0 1 |
||
92 | jelle | 10 | author=Tibor Palinkas |
138 | jelle | 11 | T 4100 11100 9 10 0 0 0 0 1 |
12 | description=NXP 16/32-bit ARM926EJ-S microcontroller |
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13 | T 4100 11300 9 10 0 0 0 0 1 |
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14 | documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf |
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146 | jelle | 15 | T 4300 10300 5 10 1 1 0 6 1 |
138 | jelle | 16 | block=RAM |
146 | jelle | 17 | T 500 10300 5 10 1 1 0 0 1 |
138 | jelle | 18 | device=LPC3180FEL320 |
146 | jelle | 19 | T 500 10500 5 10 1 1 0 0 1 |
138 | jelle | 20 | footprint=SOT824 |
146 | jelle | 21 | T 500 10700 5 10 1 1 0 0 1 |
92 | jelle | 22 | refdes=U? |
146 | jelle | 23 | P 0 7200 500 7200 1 0 0 |
92 | jelle | 24 | { |
146 | jelle | 25 | T 550 7200 9 10 1 1 0 1 1 |
92 | jelle | 26 | pinlabel=RAM_A[09] |
146 | jelle | 27 | T 400 7250 5 8 1 1 0 6 1 |
92 | jelle | 28 | pinnumber=AA23 |
146 | jelle | 29 | T 400 7250 5 8 0 1 0 6 1 |
92 | jelle | 30 | pinseq=AA23 |
31 | } |
||
146 | jelle | 32 | P 0 9900 500 9900 1 0 0 |
92 | jelle | 33 | { |
146 | jelle | 34 | T 550 9900 9 10 1 1 0 1 1 |
92 | jelle | 35 | pinlabel=RAM_A[00] |
146 | jelle | 36 | T 400 9950 5 8 1 1 0 6 1 |
92 | jelle | 37 | pinnumber=AD22 |
146 | jelle | 38 | T 400 9950 5 8 0 1 0 6 1 |
92 | jelle | 39 | pinseq=AD22 |
40 | } |
||
146 | jelle | 41 | P 4800 3600 4300 3600 1 0 0 |
92 | jelle | 42 | { |
146 | jelle | 43 | T 4250 3600 9 10 1 1 0 7 1 |
92 | jelle | 44 | pinlabel=RAM_D[21] |
146 | jelle | 45 | T 4400 3650 5 8 1 1 0 0 1 |
92 | jelle | 46 | pinnumber=H24 |
146 | jelle | 47 | T 4400 3650 5 8 0 1 0 0 1 |
92 | jelle | 48 | pinseq=H24 |
49 | } |
||
146 | jelle | 50 | P 0 6300 500 6300 1 0 0 |
92 | jelle | 51 | { |
146 | jelle | 52 | T 550 6300 9 10 1 1 0 1 1 |
92 | jelle | 53 | pinlabel=RAM_A[12] |
146 | jelle | 54 | T 400 6350 5 8 1 1 0 6 1 |
92 | jelle | 55 | pinnumber=Y23 |
146 | jelle | 56 | T 400 6350 5 8 0 1 0 6 1 |
92 | jelle | 57 | pinseq=Y23 |
58 | } |
||
146 | jelle | 59 | P 0 3600 500 3600 1 0 0 |
92 | jelle | 60 | { |
146 | jelle | 61 | T 550 3600 9 10 1 1 0 1 1 |
92 | jelle | 62 | pinlabel=RAM_CAS_N |
146 | jelle | 63 | T 400 3650 5 8 1 1 0 6 1 |
92 | jelle | 64 | pinnumber=V23 |
146 | jelle | 65 | T 400 3650 5 8 0 1 0 6 1 |
92 | jelle | 66 | pinseq=V23 |
67 | } |
||
146 | jelle | 68 | P 4800 2100 4300 2100 1 0 0 |
92 | jelle | 69 | { |
146 | jelle | 70 | T 4250 2100 9 10 1 1 0 7 1 |
92 | jelle | 71 | pinlabel=RAM_D[26] |
146 | jelle | 72 | T 4400 2150 5 8 1 1 0 0 1 |
92 | jelle | 73 | pinnumber=H23 |
146 | jelle | 74 | T 4400 2150 5 8 0 1 0 0 1 |
92 | jelle | 75 | pinseq=H23 |
76 | } |
||
146 | jelle | 77 | P 4800 5700 4300 5700 1 0 0 |
92 | jelle | 78 | { |
146 | jelle | 79 | T 4250 5700 9 10 1 1 0 7 1 |
92 | jelle | 80 | pinlabel=RAM_D[14] |
146 | jelle | 81 | T 4400 5750 5 8 1 1 0 0 1 |
92 | jelle | 82 | pinnumber=M23 |
146 | jelle | 83 | T 4400 5750 5 8 0 1 0 0 1 |
92 | jelle | 84 | pinseq=M23 |
85 | } |
||
146 | jelle | 86 | P 0 2700 500 2700 1 0 0 |
92 | jelle | 87 | { |
146 | jelle | 88 | T 550 2700 9 10 1 1 0 1 1 |
92 | jelle | 89 | pinlabel=RAM_CLKIN |
146 | jelle | 90 | T 400 2750 5 8 1 1 0 6 1 |
92 | jelle | 91 | pinnumber=T21 |
146 | jelle | 92 | T 400 2750 5 8 0 1 0 6 1 |
92 | jelle | 93 | pinseq=T21 |
94 | } |
||
146 | jelle | 95 | P 4800 8400 4300 8400 1 0 0 |
92 | jelle | 96 | { |
146 | jelle | 97 | T 4250 8400 9 10 1 1 0 7 1 |
92 | jelle | 98 | pinlabel=RAM_D[05] |
146 | jelle | 99 | T 4400 8450 5 8 1 1 0 0 1 |
92 | jelle | 100 | pinnumber=R23 |
146 | jelle | 101 | T 4400 8450 5 8 0 1 0 0 1 |
92 | jelle | 102 | pinseq=R23 |
103 | } |
||
146 | jelle | 104 | P 4800 9900 4300 9900 1 0 0 |
92 | jelle | 105 | { |
146 | jelle | 106 | T 4250 9900 9 10 1 1 0 7 1 |
92 | jelle | 107 | pinlabel=RAM_D[00] |
146 | jelle | 108 | T 4400 9950 5 8 1 1 0 0 1 |
92 | jelle | 109 | pinnumber=T23 |
146 | jelle | 110 | T 4400 9950 5 8 0 1 0 0 1 |
92 | jelle | 111 | pinseq=T23 |
112 | } |
||
146 | jelle | 113 | P 0 6900 500 6900 1 0 0 |
92 | jelle | 114 | { |
146 | jelle | 115 | T 550 6900 9 10 1 1 0 1 1 |
92 | jelle | 116 | pinlabel=RAM_A[10] |
146 | jelle | 117 | T 400 6950 5 8 1 1 0 6 1 |
92 | jelle | 118 | pinnumber=Y22 |
146 | jelle | 119 | T 400 6950 5 8 0 1 0 6 1 |
92 | jelle | 120 | pinseq=Y22 |
121 | } |
||
146 | jelle | 122 | P 0 4500 500 4500 1 0 0 |
92 | jelle | 123 | { |
146 | jelle | 124 | T 550 4500 9 10 1 1 0 1 1 |
92 | jelle | 125 | pinlabel=RAM_DQM[2] |
146 | jelle | 126 | T 400 4550 5 8 1 1 0 6 1 |
92 | jelle | 127 | pinnumber=V21 |
146 | jelle | 128 | T 400 4550 5 8 0 1 0 6 1 |
92 | jelle | 129 | pinseq=V21 |
130 | } |
||
146 | jelle | 131 | P 4800 4200 4300 4200 1 0 0 |
92 | jelle | 132 | { |
146 | jelle | 133 | T 4250 4200 9 10 1 1 0 7 1 |
92 | jelle | 134 | pinlabel=RAM_D[19] |
146 | jelle | 135 | T 4400 4250 5 8 1 1 0 0 1 |
92 | jelle | 136 | pinnumber=H21 |
146 | jelle | 137 | T 4400 4250 5 8 0 1 0 0 1 |
92 | jelle | 138 | pinseq=H21 |
139 | } |
||
146 | jelle | 140 | P 4800 600 4300 600 1 0 0 |
92 | jelle | 141 | { |
146 | jelle | 142 | T 4250 600 9 10 1 1 0 7 1 |
92 | jelle | 143 | pinlabel=RAM_D[31] |
146 | jelle | 144 | T 4400 650 5 8 1 1 0 0 1 |
92 | jelle | 145 | pinnumber=E24 |
146 | jelle | 146 | T 4400 650 5 8 0 1 0 0 1 |
92 | jelle | 147 | pinseq=E24 |
148 | } |
||
146 | jelle | 149 | P 4800 8700 4300 8700 1 0 0 |
92 | jelle | 150 | { |
146 | jelle | 151 | T 4250 8700 9 10 1 1 0 7 1 |
92 | jelle | 152 | pinlabel=RAM_D[04] |
146 | jelle | 153 | T 4400 8750 5 8 1 1 0 0 1 |
92 | jelle | 154 | pinnumber=P21 |
146 | jelle | 155 | T 4400 8750 5 8 0 1 0 0 1 |
92 | jelle | 156 | pinseq=P21 |
157 | } |
||
146 | jelle | 158 | P 4800 2400 4300 2400 1 0 0 |
92 | jelle | 159 | { |
146 | jelle | 160 | T 4250 2400 9 10 1 1 0 7 1 |
92 | jelle | 161 | pinlabel=RAM_D[25] |
146 | jelle | 162 | T 4400 2450 5 8 1 1 0 0 1 |
92 | jelle | 163 | pinnumber=J21 |
146 | jelle | 164 | T 4400 2450 5 8 0 1 0 0 1 |
92 | jelle | 165 | pinseq=J21 |
166 | } |
||
146 | jelle | 167 | P 0 3300 500 3300 1 0 0 |
92 | jelle | 168 | { |
146 | jelle | 169 | T 550 3300 9 10 1 1 0 1 1 |
92 | jelle | 170 | pinlabel=RAM_RAS_N |
146 | jelle | 171 | T 400 3350 5 8 1 1 0 6 1 |
92 | jelle | 172 | pinnumber=U21 |
146 | jelle | 173 | T 400 3350 5 8 0 1 0 6 1 |
92 | jelle | 174 | pinseq=U21 |
175 | } |
||
146 | jelle | 176 | P 0 6000 500 6000 1 0 0 |
92 | jelle | 177 | { |
146 | jelle | 178 | T 550 6000 9 10 1 1 0 1 1 |
92 | jelle | 179 | pinlabel=RAM_A[13] |
146 | jelle | 180 | T 400 6050 5 8 1 1 0 6 1 |
92 | jelle | 181 | pinnumber=AA24 |
146 | jelle | 182 | T 400 6050 5 8 0 1 0 6 1 |
92 | jelle | 183 | pinseq=AA24 |
184 | } |
||
146 | jelle | 185 | P 4800 1200 4300 1200 1 0 0 |
92 | jelle | 186 | { |
146 | jelle | 187 | T 4250 1200 9 10 1 1 0 7 1 |
92 | jelle | 188 | pinlabel=RAM_D[29] |
146 | jelle | 189 | T 4400 1250 5 8 1 1 0 0 1 |
92 | jelle | 190 | pinnumber=F21 |
146 | jelle | 191 | T 4400 1250 5 8 0 1 0 0 1 |
92 | jelle | 192 | pinseq=F21 |
193 | } |
||
146 | jelle | 194 | P 0 2100 500 2100 1 0 0 |
92 | jelle | 195 | { |
146 | jelle | 196 | T 550 2100 9 10 1 1 0 1 1 |
92 | jelle | 197 | pinlabel=RAM_CKE |
146 | jelle | 198 | T 400 2150 5 8 1 1 0 6 1 |
92 | jelle | 199 | pinnumber=U24 |
146 | jelle | 200 | T 400 2150 5 8 0 1 0 6 1 |
92 | jelle | 201 | pinseq=U24 |
202 | } |
||
146 | jelle | 203 | P 0 2400 500 2400 1 0 0 |
92 | jelle | 204 | { |
146 | jelle | 205 | T 550 2400 9 10 1 1 0 1 1 |
92 | jelle | 206 | pinlabel=RAM_CLK |
146 | jelle | 207 | T 400 2450 5 8 1 1 0 6 1 |
92 | jelle | 208 | pinnumber=U23 |
146 | jelle | 209 | T 400 2450 5 8 0 1 0 6 1 |
92 | jelle | 210 | pinseq=U23 |
211 | } |
||
146 | jelle | 212 | P 0 9000 500 9000 1 0 0 |
92 | jelle | 213 | { |
146 | jelle | 214 | T 550 9000 9 10 1 1 0 1 1 |
92 | jelle | 215 | pinlabel=RAM_A[03] |
146 | jelle | 216 | T 400 9050 5 8 1 1 0 6 1 |
92 | jelle | 217 | pinnumber=AD24 |
146 | jelle | 218 | T 400 9050 5 8 0 1 0 6 1 |
92 | jelle | 219 | pinseq=AD24 |
220 | } |
||
146 | jelle | 221 | P 0 8700 500 8700 1 0 0 |
92 | jelle | 222 | { |
146 | jelle | 223 | T 550 8700 9 10 1 1 0 1 1 |
92 | jelle | 224 | pinlabel=RAM_A[04] |
146 | jelle | 225 | T 400 8750 5 8 1 1 0 6 1 |
92 | jelle | 226 | pinnumber=AC22 |
146 | jelle | 227 | T 400 8750 5 8 0 1 0 6 1 |
92 | jelle | 228 | pinseq=AC22 |
229 | } |
||
146 | jelle | 230 | P 4800 2700 4300 2700 1 0 0 |
92 | jelle | 231 | { |
146 | jelle | 232 | T 4250 2700 9 10 1 1 0 7 1 |
92 | jelle | 233 | pinlabel=RAM_D[24] |
146 | jelle | 234 | T 4400 2750 5 8 1 1 0 0 1 |
92 | jelle | 235 | pinnumber=G23 |
146 | jelle | 236 | T 4400 2750 5 8 0 1 0 0 1 |
92 | jelle | 237 | pinseq=G23 |
238 | } |
||
146 | jelle | 239 | P 4800 5400 4300 5400 1 0 0 |
92 | jelle | 240 | { |
146 | jelle | 241 | T 4250 5400 9 10 1 1 0 7 1 |
92 | jelle | 242 | pinlabel=RAM_D[15] |
146 | jelle | 243 | T 4400 5450 5 8 1 1 0 0 1 |
92 | jelle | 244 | pinnumber=L24 |
146 | jelle | 245 | T 4400 5450 5 8 0 1 0 0 1 |
92 | jelle | 246 | pinseq=L24 |
247 | } |
||
146 | jelle | 248 | P 0 4200 500 4200 1 0 0 |
92 | jelle | 249 | { |
146 | jelle | 250 | T 550 4200 9 10 1 1 0 1 1 |
92 | jelle | 251 | pinlabel=RAM_DQM[3] |
146 | jelle | 252 | T 400 4250 5 8 1 1 0 6 1 |
92 | jelle | 253 | pinnumber=W24 |
146 | jelle | 254 | T 400 4250 5 8 0 1 0 6 1 |
92 | jelle | 255 | pinseq=W24 |
256 | } |
||
146 | jelle | 257 | P 4800 900 4300 900 1 0 0 |
92 | jelle | 258 | { |
146 | jelle | 259 | T 4250 900 9 10 1 1 0 7 1 |
92 | jelle | 260 | pinlabel=RAM_D[30] |
146 | jelle | 261 | T 4400 950 5 8 1 1 0 0 1 |
92 | jelle | 262 | pinnumber=E23 |
146 | jelle | 263 | T 4400 950 5 8 0 1 0 0 1 |
92 | jelle | 264 | pinseq=E23 |
265 | } |
||
146 | jelle | 266 | P 4800 7800 4300 7800 1 0 0 |
92 | jelle | 267 | { |
146 | jelle | 268 | T 4250 7800 9 10 1 1 0 7 1 |
92 | jelle | 269 | pinlabel=RAM_D[08] |
146 | jelle | 270 | T 4400 7850 5 8 1 1 0 0 1 |
92 | jelle | 271 | pinnumber=P23 |
146 | jelle | 272 | T 4400 7850 5 8 0 1 0 0 1 |
92 | jelle | 273 | pinseq=P23 |
274 | } |
||
146 | jelle | 275 | P 0 7800 500 7800 1 0 0 |
92 | jelle | 276 | { |
146 | jelle | 277 | T 550 7800 9 10 1 1 0 1 1 |
92 | jelle | 278 | pinlabel=RAM_A[07] |
146 | jelle | 279 | T 400 7850 5 8 1 1 0 6 1 |
92 | jelle | 280 | pinnumber=AB22 |
146 | jelle | 281 | T 400 7850 5 8 0 1 0 6 1 |
92 | jelle | 282 | pinseq=AB22 |
283 | } |
||
146 | jelle | 284 | P 4800 6000 4300 6000 1 0 0 |
92 | jelle | 285 | { |
146 | jelle | 286 | T 4250 6000 9 10 1 1 0 7 1 |
92 | jelle | 287 | pinlabel=RAM_D[13] |
146 | jelle | 288 | T 4400 6050 5 8 1 1 0 0 1 |
92 | jelle | 289 | pinnumber=L22 |
146 | jelle | 290 | T 4400 6050 5 8 0 1 0 0 1 |
92 | jelle | 291 | pinseq=L22 |
292 | } |
||
146 | jelle | 293 | P 4800 7500 4300 7500 1 0 0 |
92 | jelle | 294 | { |
146 | jelle | 295 | T 4250 7500 9 10 1 1 0 7 1 |
92 | jelle | 296 | pinlabel=RAM_D[07] |
146 | jelle | 297 | T 4400 7550 5 8 1 1 0 0 1 |
92 | jelle | 298 | pinnumber=N21 |
146 | jelle | 299 | T 4400 7550 5 8 0 1 0 0 1 |
92 | jelle | 300 | pinseq=N21 |
301 | } |
||
146 | jelle | 302 | P 4800 9300 4300 9300 1 0 0 |
92 | jelle | 303 | { |
146 | jelle | 304 | T 4250 9300 9 10 1 1 0 7 1 |
92 | jelle | 305 | pinlabel=RAM_D[02] |
146 | jelle | 306 | T 4400 9350 5 8 1 1 0 0 1 |
92 | jelle | 307 | pinnumber=T24 |
146 | jelle | 308 | T 4400 9350 5 8 0 1 0 0 1 |
92 | jelle | 309 | pinseq=T24 |
310 | } |
||
146 | jelle | 311 | P 0 5100 500 5100 1 0 0 |
92 | jelle | 312 | { |
146 | jelle | 313 | T 550 5100 9 10 1 1 0 1 1 |
92 | jelle | 314 | pinlabel=RAM_DQM[0] |
146 | jelle | 315 | T 400 5150 5 8 1 1 0 6 1 |
92 | jelle | 316 | pinnumber=Y24 |
146 | jelle | 317 | T 400 5150 5 8 0 1 0 6 1 |
92 | jelle | 318 | pinseq=Y24 |
319 | } |
||
146 | jelle | 320 | P 0 5700 500 5700 1 0 0 |
92 | jelle | 321 | { |
146 | jelle | 322 | T 550 5700 9 10 1 1 0 1 1 |
92 | jelle | 323 | pinlabel=RAM_A[14] |
146 | jelle | 324 | T 400 5750 5 8 1 1 0 6 1 |
92 | jelle | 325 | pinnumber=W21 |
146 | jelle | 326 | T 400 5750 5 8 0 1 0 6 1 |
92 | jelle | 327 | pinseq=W21 |
328 | } |
||
146 | jelle | 329 | P 4800 6300 4300 6300 1 0 0 |
92 | jelle | 330 | { |
146 | jelle | 331 | T 4250 6300 9 10 1 1 0 7 1 |
92 | jelle | 332 | pinlabel=RAM_D[12] |
146 | jelle | 333 | T 4400 6350 5 8 1 1 0 0 1 |
92 | jelle | 334 | pinnumber=M24 |
146 | jelle | 335 | T 4400 6350 5 8 0 1 0 0 1 |
92 | jelle | 336 | pinseq=M24 |
337 | } |
||
146 | jelle | 338 | P 4800 1800 4300 1800 1 0 0 |
92 | jelle | 339 | { |
146 | jelle | 340 | T 4250 1800 9 10 1 1 0 7 1 |
92 | jelle | 341 | pinlabel=RAM_D[27] |
146 | jelle | 342 | T 4400 1850 5 8 1 1 0 0 1 |
92 | jelle | 343 | pinnumber=G24 |
146 | jelle | 344 | T 4400 1850 5 8 0 1 0 0 1 |
92 | jelle | 345 | pinseq=G24 |
346 | } |
||
146 | jelle | 347 | P 0 8400 500 8400 1 0 0 |
92 | jelle | 348 | { |
146 | jelle | 349 | T 550 8400 9 10 1 1 0 1 1 |
92 | jelle | 350 | pinlabel=RAM_A[05] |
146 | jelle | 351 | T 400 8450 5 8 1 1 0 6 1 |
92 | jelle | 352 | pinnumber=AA21 |
146 | jelle | 353 | T 400 8450 5 8 0 1 0 6 1 |
92 | jelle | 354 | pinseq=AA21 |
355 | } |
||
146 | jelle | 356 | P 4800 5100 4300 5100 1 0 0 |
92 | jelle | 357 | { |
146 | jelle | 358 | T 4250 5100 9 10 1 1 0 7 1 |
92 | jelle | 359 | pinlabel=RAM_D[16]/DDR_DQS0 |
146 | jelle | 360 | T 4400 5150 5 8 1 1 0 0 1 |
92 | jelle | 361 | pinnumber=L23 |
146 | jelle | 362 | T 4400 5150 5 8 0 1 0 0 1 |
92 | jelle | 363 | pinseq=L23 |
364 | } |
||
146 | jelle | 365 | P 4800 9000 4300 9000 1 0 0 |
92 | jelle | 366 | { |
146 | jelle | 367 | T 4250 9000 9 10 1 1 0 7 1 |
92 | jelle | 368 | pinlabel=RAM_D[03] |
146 | jelle | 369 | T 4400 9050 5 8 1 1 0 0 1 |
92 | jelle | 370 | pinnumber=R24 |
146 | jelle | 371 | T 4400 9050 5 8 0 1 0 0 1 |
92 | jelle | 372 | pinseq=R24 |
373 | } |
||
146 | jelle | 374 | P 0 9600 500 9600 1 0 0 |
92 | jelle | 375 | { |
146 | jelle | 376 | T 550 9600 9 10 1 1 0 1 1 |
92 | jelle | 377 | pinlabel=RAM_A[01] |
146 | jelle | 378 | T 400 9650 5 8 1 1 0 6 1 |
92 | jelle | 379 | pinnumber=AB20 |
146 | jelle | 380 | T 400 9650 5 8 0 1 0 6 1 |
92 | jelle | 381 | pinseq=AB20 |
382 | } |
||
146 | jelle | 383 | P 4800 1500 4300 1500 1 0 0 |
92 | jelle | 384 | { |
146 | jelle | 385 | T 4250 1500 9 10 1 1 0 7 1 |
92 | jelle | 386 | pinlabel=RAM_D[28] |
146 | jelle | 387 | T 4400 1550 5 8 1 1 0 0 1 |
92 | jelle | 388 | pinnumber=F24 |
146 | jelle | 389 | T 4400 1550 5 8 0 1 0 0 1 |
92 | jelle | 390 | pinseq=F24 |
391 | } |
||
146 | jelle | 392 | P 0 8100 500 8100 1 0 0 |
92 | jelle | 393 | { |
146 | jelle | 394 | T 550 8100 9 10 1 1 0 1 1 |
92 | jelle | 395 | pinlabel=RAM_A[06] |
146 | jelle | 396 | T 400 8150 5 8 1 1 0 6 1 |
92 | jelle | 397 | pinnumber=AC23 |
146 | jelle | 398 | T 400 8150 5 8 0 1 0 6 1 |
92 | jelle | 399 | pinseq=AC23 |
400 | } |
||
146 | jelle | 401 | P 4800 6600 4300 6600 1 0 0 |
92 | jelle | 402 | { |
146 | jelle | 403 | T 4250 6600 9 10 1 1 0 7 1 |
92 | jelle | 404 | pinlabel=RAM_D[11] |
146 | jelle | 405 | T 4400 6650 5 8 1 1 0 0 1 |
92 | jelle | 406 | pinnumber=N23 |
146 | jelle | 407 | T 4400 6650 5 8 0 1 0 0 1 |
92 | jelle | 408 | pinseq=N23 |
409 | } |
||
146 | jelle | 410 | P 4800 7200 4300 7200 1 0 0 |
92 | jelle | 411 | { |
146 | jelle | 412 | T 4250 7200 9 10 1 1 0 7 1 |
92 | jelle | 413 | pinlabel=RAM_D[09] |
146 | jelle | 414 | T 4400 7250 5 8 1 1 0 0 1 |
92 | jelle | 415 | pinnumber=N24 |
146 | jelle | 416 | T 4400 7250 5 8 0 1 0 0 1 |
92 | jelle | 417 | pinseq=N24 |
418 | } |
||
146 | jelle | 419 | P 0 9300 500 9300 1 0 0 |
92 | jelle | 420 | { |
146 | jelle | 421 | T 550 9300 9 10 1 1 0 1 1 |
92 | jelle | 422 | pinlabel=RAM_A[02] |
146 | jelle | 423 | T 400 9350 5 8 1 1 0 6 1 |
92 | jelle | 424 | pinnumber=AD23 |
146 | jelle | 425 | T 400 9350 5 8 0 1 0 6 1 |
92 | jelle | 426 | pinseq=AD23 |
427 | } |
||
146 | jelle | 428 | P 0 4800 500 4800 1 0 0 |
92 | jelle | 429 | { |
146 | jelle | 430 | T 550 4800 9 10 1 1 0 1 1 |
92 | jelle | 431 | pinlabel=RAM_DQM[1] |
146 | jelle | 432 | T 400 4850 5 8 1 1 0 6 1 |
92 | jelle | 433 | pinnumber=W23 |
146 | jelle | 434 | T 400 4850 5 8 0 1 0 6 1 |
92 | jelle | 435 | pinseq=W23 |
436 | } |
||
146 | jelle | 437 | P 4800 6900 4300 6900 1 0 0 |
92 | jelle | 438 | { |
146 | jelle | 439 | T 4250 6900 9 10 1 1 0 7 1 |
92 | jelle | 440 | pinlabel=RAM_D[10] |
146 | jelle | 441 | T 4400 6950 5 8 1 1 0 0 1 |
92 | jelle | 442 | pinnumber=M22 |
146 | jelle | 443 | T 4400 6950 5 8 0 1 0 0 1 |
92 | jelle | 444 | pinseq=M22 |
445 | } |
||
146 | jelle | 446 | P 4800 4500 4300 4500 1 0 0 |
92 | jelle | 447 | { |
146 | jelle | 448 | T 4250 4500 9 10 1 1 0 7 1 |
92 | jelle | 449 | pinlabel=RAM_D[18]/DDR_NCLK |
146 | jelle | 450 | T 4400 4550 5 8 1 1 0 0 1 |
92 | jelle | 451 | pinnumber=K24 |
146 | jelle | 452 | T 4400 4550 5 8 0 1 0 0 1 |
92 | jelle | 453 | pinseq=K24 |
454 | } |
||
146 | jelle | 455 | P 4800 3900 4300 3900 1 0 0 |
92 | jelle | 456 | { |
146 | jelle | 457 | T 4250 3900 9 10 1 1 0 7 1 |
92 | jelle | 458 | pinlabel=RAM_D[20] |
146 | jelle | 459 | T 4400 3950 5 8 1 1 0 0 1 |
92 | jelle | 460 | pinnumber=J24 |
146 | jelle | 461 | T 4400 3950 5 8 0 1 0 0 1 |
92 | jelle | 462 | pinseq=J24 |
463 | } |
||
146 | jelle | 464 | P 0 7500 500 7500 1 0 0 |
92 | jelle | 465 | { |
146 | jelle | 466 | T 550 7500 9 10 1 1 0 1 1 |
92 | jelle | 467 | pinlabel=RAM_A[08] |
146 | jelle | 468 | T 400 7550 5 8 1 1 0 6 1 |
92 | jelle | 469 | pinnumber=AB23 |
146 | jelle | 470 | T 400 7550 5 8 0 1 0 6 1 |
92 | jelle | 471 | pinseq=AB23 |
472 | } |
||
146 | jelle | 473 | P 0 6600 500 6600 1 0 0 |
92 | jelle | 474 | { |
146 | jelle | 475 | T 550 6600 9 10 1 1 0 1 1 |
92 | jelle | 476 | pinlabel=RAM_A[11] |
146 | jelle | 477 | T 400 6650 5 8 1 1 0 6 1 |
92 | jelle | 478 | pinnumber=AB24 |
146 | jelle | 479 | T 400 6650 5 8 0 1 0 6 1 |
92 | jelle | 480 | pinseq=AB24 |
481 | } |
||
146 | jelle | 482 | P 4800 3000 4300 3000 1 0 0 |
92 | jelle | 483 | { |
146 | jelle | 484 | T 4250 3000 9 10 1 1 0 7 1 |
92 | jelle | 485 | pinlabel=RAM_D[23] |
146 | jelle | 486 | T 4400 3050 5 8 1 1 0 0 1 |
92 | jelle | 487 | pinnumber=H22 |
146 | jelle | 488 | T 4400 3050 5 8 0 1 0 0 1 |
92 | jelle | 489 | pinseq=H22 |
490 | } |
||
146 | jelle | 491 | P 0 1200 500 1200 1 0 0 |
92 | jelle | 492 | { |
146 | jelle | 493 | T 550 1200 9 10 1 1 0 1 1 |
92 | jelle | 494 | pinlabel=RAM_CS_N |
146 | jelle | 495 | T 400 1250 5 8 1 1 0 6 1 |
92 | jelle | 496 | pinnumber=V24 |
146 | jelle | 497 | T 400 1250 5 8 0 1 0 6 1 |
92 | jelle | 498 | pinseq=V24 |
499 | } |
||
146 | jelle | 500 | P 4800 4800 4300 4800 1 0 0 |
92 | jelle | 501 | { |
146 | jelle | 502 | T 4250 4800 9 10 1 1 0 7 1 |
92 | jelle | 503 | pinlabel=RAM_D[17]/DDR_DQS1 |
146 | jelle | 504 | T 4400 4850 5 8 1 1 0 0 1 |
92 | jelle | 505 | pinnumber=L21 |
146 | jelle | 506 | T 4400 4850 5 8 0 1 0 0 1 |
92 | jelle | 507 | pinseq=L21 |
508 | } |
||
146 | jelle | 509 | P 4800 8100 4300 8100 1 0 0 |
92 | jelle | 510 | { |
146 | jelle | 511 | T 4250 8100 9 10 1 1 0 7 1 |
92 | jelle | 512 | pinlabel=RAM_D[06] |
146 | jelle | 513 | T 4400 8150 5 8 1 1 0 0 1 |
92 | jelle | 514 | pinnumber=P24 |
146 | jelle | 515 | T 4400 8150 5 8 0 1 0 0 1 |
92 | jelle | 516 | pinseq=P24 |
517 | } |
||
146 | jelle | 518 | P 4800 9600 4300 9600 1 0 0 |
92 | jelle | 519 | { |
146 | jelle | 520 | T 4250 9600 9 10 1 1 0 7 1 |
92 | jelle | 521 | pinlabel=RAM_D[01] |
146 | jelle | 522 | T 4400 9650 5 8 1 1 0 0 1 |
92 | jelle | 523 | pinnumber=T22 |
146 | jelle | 524 | T 4400 9650 5 8 0 1 0 0 1 |
92 | jelle | 525 | pinseq=T22 |
526 | } |
||
146 | jelle | 527 | P 4800 3300 4300 3300 1 0 0 |
92 | jelle | 528 | { |
146 | jelle | 529 | T 4250 3300 9 10 1 1 0 7 1 |
92 | jelle | 530 | pinlabel=RAM_D[22] |
146 | jelle | 531 | T 4400 3350 5 8 1 1 0 0 1 |
92 | jelle | 532 | pinnumber=K23 |
146 | jelle | 533 | T 4400 3350 5 8 0 1 0 0 1 |
92 | jelle | 534 | pinseq=K23 |
535 | } |
||
146 | jelle | 536 | P 0 1500 500 1500 1 0 0 |
92 | jelle | 537 | { |
146 | jelle | 538 | T 550 1500 9 10 1 1 0 1 1 |
92 | jelle | 539 | pinlabel=RAM_WR_N |
146 | jelle | 540 | T 400 1550 5 8 1 1 0 6 1 |
92 | jelle | 541 | pinnumber=V22 |
146 | jelle | 542 | T 400 1550 5 8 0 1 0 6 1 |
92 | jelle | 543 | pinseq=V22 |
544 | } |