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Rev Author Line No. Line
92 jelle 1 
v 20060123 1
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B 500 300 3100 3300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
3 
T 3400 3700 9 10 0 0 0 0 1
138 jelle 4 
uselicense=unlimited
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T 3400 3900 9 10 0 0 0 0 1
92 jelle 6 
distlicense=GPL (v2 or any later version)
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T 3400 4100 9 10 0 0 0 0 1
138 jelle 8 
copyright=2008 Tibor Palinkas
207 jelle 9 
T 3400 4300 9 10 0 0 0 0 1
92 jelle 10 
author=Tibor Palinkas
207 jelle 11 
T 3400 4500 9 10 0 0 0 0 1
138 jelle 12 
description=NXP 16/32-bit ARM926EJ-S microcontroller
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T 3400 4700 9 10 0 0 0 0 1
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documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf
207 jelle 15 
T 3600 3700 5 10 1 1 0 6 1
138 jelle 16 
block=VDD (CORE)
207 jelle 17 
T 500 3700 5 10 1 1 0 0 1
138 jelle 18 
device=LPC3180FEL320
207 jelle 19 
T 500 3900 5 10 1 1 0 0 1
138 jelle 20 
footprint=SOT824
207 jelle 21 
T 500 4100 5 10 1 1 0 0 1
92 jelle 22 
refdes=U?
207 jelle 23 
P 0 600 500 600 1 0 0
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{
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T 550 600 9 10 1 1 0 1 1
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pinlabel=VDD_COREFXD12_02
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T 400 650 5 8 1 1 0 6 1
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pinnumber=D18
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T 400 650 5 8 0 1 0 6 1
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pinseq=D18
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}
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P 0 3000 500 3000 1 0 0
92 jelle 33 
{
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T 550 3000 9 10 1 1 0 1 1
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pinlabel=VDD_CORE12_02
207 jelle 36 
T 400 3050 5 8 1 1 0 6 1
92 jelle 37 
pinnumber=D6
207 jelle 38 
T 400 3050 5 8 0 1 0 6 1
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pinseq=D6
40 
}
207 jelle 41 
P 0 2700 500 2700 1 0 0
92 jelle 42 
{
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T 550 2700 9 10 1 1 0 1 1
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pinlabel=VDD_CORE12_03
207 jelle 45 
T 400 2750 5 8 1 1 0 6 1
92 jelle 46 
pinnumber=K21
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T 400 2750 5 8 0 1 0 6 1
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pinseq=K21
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}
207 jelle 50 
P 0 1500 500 1500 1 0 0
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{
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T 550 1500 9 10 1 1 0 1 1
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pinlabel=VDD_CORE12_08
207 jelle 54 
T 400 1550 5 8 1 1 0 6 1
92 jelle 55 
pinnumber=AB18
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T 400 1550 5 8 0 1 0 6 1
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pinseq=AB18
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}
207 jelle 59 
P 0 900 500 900 1 0 0
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{
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T 550 900 9 10 1 1 0 1 1
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pinlabel=VDD_COREFXD12_01
207 jelle 63 
T 400 950 5 8 1 1 0 6 1
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pinnumber=C10
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T 400 950 5 8 0 1 0 6 1
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pinseq=C10
67 
}
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P 0 2400 500 2400 1 0 0
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{
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T 550 2400 9 10 1 1 0 1 1
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pinlabel=VDD_CORE12_05
207 jelle 72 
T 400 2450 5 8 1 1 0 6 1
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pinnumber=L3
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T 400 2450 5 8 0 1 0 6 1
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pinseq=L3
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}
207 jelle 77 
P 0 1800 500 1800 1 0 0
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{
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T 550 1800 9 10 1 1 0 1 1
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pinlabel=VDD_CORE12_07
207 jelle 81 
T 400 1850 5 8 1 1 0 6 1
92 jelle 82 
pinnumber=AB6
207 jelle 83 
T 400 1850 5 8 0 1 0 6 1
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pinseq=AB6
85 
}
207 jelle 86 
P 0 2100 500 2100 1 0 0
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{
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T 550 2100 9 10 1 1 0 1 1
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pinlabel=VDD_CORE12_06
207 jelle 90 
T 400 2150 5 8 1 1 0 6 1
92 jelle 91 
pinnumber=AA12
207 jelle 92 
T 400 2150 5 8 0 1 0 6 1
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pinseq=AA12
94 
}
207 jelle 95 
P 0 3300 500 3300 1 0 0
92 jelle 96 
{
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T 550 3300 9 10 1 1 0 1 1
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pinlabel=VDD_CORE12_01
207 jelle 99 
T 400 3350 5 8 1 1 0 6 1
92 jelle 100 
pinnumber=AA2
207 jelle 101 
T 400 3350 5 8 0 1 0 6 1
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pinseq=AA2
103 
}