Rev 138 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
92 | jelle | 1 | v 20060123 1 |
146 | jelle | 2 | B 500 300 1800 3600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
138 | jelle | 3 | T 2100 4000 9 10 0 0 0 0 1 |
4 | uselicense=unlimited |
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5 | T 2100 4200 9 10 0 0 0 0 1 |
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92 | jelle | 6 | distlicense=GPL (v2 or any later version) |
138 | jelle | 7 | T 2100 4400 9 10 0 0 0 0 1 |
8 | copyright=2008 Tibor Palinkas |
||
9 | T 2100 4600 9 10 0 0 0 0 1 |
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92 | jelle | 10 | author=Tibor Palinkas |
138 | jelle | 11 | T 2100 4800 9 10 0 0 0 0 1 |
12 | description=NXP 16/32-bit ARM926EJ-S microcontroller |
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13 | T 2100 5000 9 10 0 0 0 0 1 |
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14 | documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf |
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146 | jelle | 15 | T 2300 4000 5 10 1 1 0 6 1 |
138 | jelle | 16 | block=VSS (RAM) |
146 | jelle | 17 | T 500 4000 5 10 1 1 0 0 1 |
138 | jelle | 18 | device=LPC3180FEL320 |
146 | jelle | 19 | T 500 4200 5 10 1 1 0 0 1 |
138 | jelle | 20 | footprint=SOT824 |
146 | jelle | 21 | T 500 4400 5 10 1 1 0 0 1 |
92 | jelle | 22 | refdes=U? |
146 | jelle | 23 | P 0 900 500 900 1 0 0 |
92 | jelle | 24 | { |
146 | jelle | 25 | T 550 900 9 10 1 1 0 1 1 |
92 | jelle | 26 | pinlabel=VSS_RAM |
146 | jelle | 27 | T 400 950 5 8 1 1 0 6 1 |
92 | jelle | 28 | pinnumber=R22 |
146 | jelle | 29 | T 400 950 5 8 0 1 0 6 1 |
92 | jelle | 30 | pinseq=R22 |
31 | } |
||
146 | jelle | 32 | P 0 2400 500 2400 1 0 0 |
92 | jelle | 33 | { |
146 | jelle | 34 | T 550 2400 9 10 1 1 0 1 1 |
92 | jelle | 35 | pinlabel=VSS_RAM |
146 | jelle | 36 | T 400 2450 5 8 1 1 0 6 1 |
92 | jelle | 37 | pinnumber=F23 |
146 | jelle | 38 | T 400 2450 5 8 0 1 0 6 1 |
92 | jelle | 39 | pinseq=F23 |
40 | } |
||
146 | jelle | 41 | P 0 1200 500 1200 1 0 0 |
92 | jelle | 42 | { |
146 | jelle | 43 | T 550 1200 9 10 1 1 0 1 1 |
92 | jelle | 44 | pinlabel=VSS_RAM |
146 | jelle | 45 | T 400 1250 5 8 1 1 0 6 1 |
92 | jelle | 46 | pinnumber=N22 |
146 | jelle | 47 | T 400 1250 5 8 0 1 0 6 1 |
92 | jelle | 48 | pinseq=N22 |
49 | } |
||
146 | jelle | 50 | P 0 2700 500 2700 1 0 0 |
92 | jelle | 51 | { |
146 | jelle | 52 | T 550 2700 9 10 1 1 0 1 1 |
92 | jelle | 53 | pinlabel=VSS_RAM |
146 | jelle | 54 | T 400 2750 5 8 1 1 0 6 1 |
92 | jelle | 55 | pinnumber=C19 |
146 | jelle | 56 | T 400 2750 5 8 0 1 0 6 1 |
92 | jelle | 57 | pinseq=C19 |
58 | } |
||
146 | jelle | 59 | P 0 3300 500 3300 1 0 0 |
92 | jelle | 60 | { |
146 | jelle | 61 | T 550 3300 9 10 1 1 0 1 1 |
92 | jelle | 62 | pinlabel=VSS_RAM |
146 | jelle | 63 | T 400 3350 5 8 1 1 0 6 1 |
92 | jelle | 64 | pinnumber=AA22 |
146 | jelle | 65 | T 400 3350 5 8 0 1 0 6 1 |
92 | jelle | 66 | pinseq=AA22 |
67 | } |
||
146 | jelle | 68 | P 0 2100 500 2100 1 0 0 |
92 | jelle | 69 | { |
146 | jelle | 70 | T 550 2100 9 10 1 1 0 1 1 |
92 | jelle | 71 | pinlabel=VSS_RAM |
146 | jelle | 72 | T 400 2150 5 8 1 1 0 6 1 |
92 | jelle | 73 | pinnumber=G22 |
146 | jelle | 74 | T 400 2150 5 8 0 1 0 6 1 |
92 | jelle | 75 | pinseq=G22 |
76 | } |
||
146 | jelle | 77 | P 0 3600 500 3600 1 0 0 |
92 | jelle | 78 | { |
146 | jelle | 79 | T 550 3600 9 10 1 1 0 1 1 |
92 | jelle | 80 | pinlabel=VSS_RAM |
146 | jelle | 81 | T 400 3650 5 8 1 1 0 6 1 |
92 | jelle | 82 | pinnumber=AB21 |
146 | jelle | 83 | T 400 3650 5 8 0 1 0 6 1 |
92 | jelle | 84 | pinseq=AB21 |
85 | } |
||
146 | jelle | 86 | P 0 3000 500 3000 1 0 0 |
92 | jelle | 87 | { |
146 | jelle | 88 | T 550 3000 9 10 1 1 0 1 1 |
92 | jelle | 89 | pinlabel=VSS_RAM |
146 | jelle | 90 | T 400 3050 5 8 1 1 0 6 1 |
92 | jelle | 91 | pinnumber=AD11 |
146 | jelle | 92 | T 400 3050 5 8 0 1 0 6 1 |
92 | jelle | 93 | pinseq=AD11 |
94 | } |
||
146 | jelle | 95 | P 0 600 500 600 1 0 0 |
92 | jelle | 96 | { |
146 | jelle | 97 | T 550 600 9 10 1 1 0 1 1 |
92 | jelle | 98 | pinlabel=VSS_RAM |
146 | jelle | 99 | T 400 650 5 8 1 1 0 6 1 |
92 | jelle | 100 | pinnumber=W22 |
146 | jelle | 101 | T 400 650 5 8 0 1 0 6 1 |
92 | jelle | 102 | pinseq=W22 |
103 | } |
||
146 | jelle | 104 | P 0 1500 500 1500 1 0 0 |
92 | jelle | 105 | { |
146 | jelle | 106 | T 550 1500 9 10 1 1 0 1 1 |
92 | jelle | 107 | pinlabel=VSS_RAM |
146 | jelle | 108 | T 400 1550 5 8 1 1 0 6 1 |
92 | jelle | 109 | pinnumber=M21 |
146 | jelle | 110 | T 400 1550 5 8 0 1 0 6 1 |
92 | jelle | 111 | pinseq=M21 |
112 | } |
||
146 | jelle | 113 | P 0 1800 500 1800 1 0 0 |
92 | jelle | 114 | { |
146 | jelle | 115 | T 550 1800 9 10 1 1 0 1 1 |
92 | jelle | 116 | pinlabel=VSS_RAM |
146 | jelle | 117 | T 400 1850 5 8 1 1 0 6 1 |
92 | jelle | 118 | pinnumber=J23 |
146 | jelle | 119 | T 400 1850 5 8 0 1 0 6 1 |
92 | jelle | 120 | pinseq=J23 |
121 | } |