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Rev 138 Rev 146
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v 20060123 1
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v 20060123 1
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B 300 300 3800 9900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 500 300 3800 9900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 4100 10300 9 10 0 0 0 0 1
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T 4100 10300 9 10 0 0 0 0 1
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uselicense=unlimited
4 
uselicense=unlimited
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T 4100 10500 9 10 0 0 0 0 1
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T 4100 10500 9 10 0 0 0 0 1
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distlicense=GPL (v2 or any later version)
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distlicense=GPL (v2 or any later version)
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T 4100 10700 9 10 0 0 0 0 1
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T 4100 10700 9 10 0 0 0 0 1
Line 10... Line 10...
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author=Tibor Palinkas
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author=Tibor Palinkas
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T 4100 11100 9 10 0 0 0 0 1
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T 4100 11100 9 10 0 0 0 0 1
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description=NXP 16/32-bit ARM926EJ-S microcontroller
12 
description=NXP 16/32-bit ARM926EJ-S microcontroller
13 
T 4100 11300 9 10 0 0 0 0 1
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T 4100 11300 9 10 0 0 0 0 1
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documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf
14 
documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf
15 
T 300 10300 5 10 1 1 0 0 1
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T 4300 10300 5 10 1 1 0 6 1
16 
block=RAM
16 
block=RAM
17 
T 300 10500 5 10 1 1 0 0 1
17 
T 500 10300 5 10 1 1 0 0 1
18 
device=LPC3180FEL320
18 
device=LPC3180FEL320
19 
T 300 10700 5 10 1 1 0 0 1
19 
T 500 10500 5 10 1 1 0 0 1
20 
footprint=SOT824
20 
footprint=SOT824
21 
T 300 10900 5 10 1 1 0 0 1
21 
T 500 10700 5 10 1 1 0 0 1
22 
refdes=U?
22 
refdes=U?
23 
P 0 7200 300 7200 1 0 0
23 
P 0 7200 500 7200 1 0 0
24 
{
24 
{
25 
T 350 7200 9 10 1 1 0 1 1
25 
T 550 7200 9 10 1 1 0 1 1
26 
pinlabel=RAM_A[09]
26 
pinlabel=RAM_A[09]
27 
T 200 7250 5 8 1 1 0 6 1
27 
T 400 7250 5 8 1 1 0 6 1
28 
pinnumber=AA23
28 
pinnumber=AA23
29 
T 200 7250 5 8 0 1 0 6 1
29 
T 400 7250 5 8 0 1 0 6 1
30 
pinseq=AA23
30 
pinseq=AA23
31 
}
31 
}
32 
P 0 9900 300 9900 1 0 0
32 
P 0 9900 500 9900 1 0 0
33 
{
33 
{
34 
T 350 9900 9 10 1 1 0 1 1
34 
T 550 9900 9 10 1 1 0 1 1
35 
pinlabel=RAM_A[00]
35 
pinlabel=RAM_A[00]
36 
T 200 9950 5 8 1 1 0 6 1
36 
T 400 9950 5 8 1 1 0 6 1
37 
pinnumber=AD22
37 
pinnumber=AD22
38 
T 200 9950 5 8 0 1 0 6 1
38 
T 400 9950 5 8 0 1 0 6 1
39 
pinseq=AD22
39 
pinseq=AD22
40 
}
40 
}
41 
P 4400 3600 4100 3600 1 0 0
41 
P 4800 3600 4300 3600 1 0 0
42 
{
42 
{
43 
T 4050 3600 9 10 1 1 0 7 1
43 
T 4250 3600 9 10 1 1 0 7 1
44 
pinlabel=RAM_D[21]
44 
pinlabel=RAM_D[21]
45 
T 4200 3650 5 8 1 1 0 0 1
45 
T 4400 3650 5 8 1 1 0 0 1
46 
pinnumber=H24
46 
pinnumber=H24
47 
T 4200 3650 5 8 0 1 0 0 1
47 
T 4400 3650 5 8 0 1 0 0 1
48 
pinseq=H24
48 
pinseq=H24
49 
}
49 
}
50 
P 0 6300 300 6300 1 0 0
50 
P 0 6300 500 6300 1 0 0
51 
{
51 
{
52 
T 350 6300 9 10 1 1 0 1 1
52 
T 550 6300 9 10 1 1 0 1 1
53 
pinlabel=RAM_A[12]
53 
pinlabel=RAM_A[12]
54 
T 200 6350 5 8 1 1 0 6 1
54 
T 400 6350 5 8 1 1 0 6 1
55 
pinnumber=Y23
55 
pinnumber=Y23
56 
T 200 6350 5 8 0 1 0 6 1
56 
T 400 6350 5 8 0 1 0 6 1
57 
pinseq=Y23
57 
pinseq=Y23
58 
}
58 
}
59 
P 0 3600 300 3600 1 0 0
59 
P 0 3600 500 3600 1 0 0
60 
{
60 
{
61 
T 350 3600 9 10 1 1 0 1 1
61 
T 550 3600 9 10 1 1 0 1 1
62 
pinlabel=RAM_CAS_N
62 
pinlabel=RAM_CAS_N
63 
T 200 3650 5 8 1 1 0 6 1
63 
T 400 3650 5 8 1 1 0 6 1
64 
pinnumber=V23
64 
pinnumber=V23
65 
T 200 3650 5 8 0 1 0 6 1
65 
T 400 3650 5 8 0 1 0 6 1
66 
pinseq=V23
66 
pinseq=V23
67 
}
67 
}
68 
P 4400 2100 4100 2100 1 0 0
68 
P 4800 2100 4300 2100 1 0 0
69 
{
69 
{
70 
T 4050 2100 9 10 1 1 0 7 1
70 
T 4250 2100 9 10 1 1 0 7 1
71 
pinlabel=RAM_D[26]
71 
pinlabel=RAM_D[26]
72 
T 4200 2150 5 8 1 1 0 0 1
72 
T 4400 2150 5 8 1 1 0 0 1
73 
pinnumber=H23
73 
pinnumber=H23
74 
T 4200 2150 5 8 0 1 0 0 1
74 
T 4400 2150 5 8 0 1 0 0 1
75 
pinseq=H23
75 
pinseq=H23
76 
}
76 
}
77 
P 4400 5700 4100 5700 1 0 0
77 
P 4800 5700 4300 5700 1 0 0
78 
{
78 
{
79 
T 4050 5700 9 10 1 1 0 7 1
79 
T 4250 5700 9 10 1 1 0 7 1
80 
pinlabel=RAM_D[14]
80 
pinlabel=RAM_D[14]
81 
T 4200 5750 5 8 1 1 0 0 1
81 
T 4400 5750 5 8 1 1 0 0 1
82 
pinnumber=M23
82 
pinnumber=M23
83 
T 4200 5750 5 8 0 1 0 0 1
83 
T 4400 5750 5 8 0 1 0 0 1
84 
pinseq=M23
84 
pinseq=M23
85 
}
85 
}
86 
P 0 2700 300 2700 1 0 0
86 
P 0 2700 500 2700 1 0 0
87 
{
87 
{
88 
T 350 2700 9 10 1 1 0 1 1
88 
T 550 2700 9 10 1 1 0 1 1
89 
pinlabel=RAM_CLKIN
89 
pinlabel=RAM_CLKIN
90 
T 200 2750 5 8 1 1 0 6 1
90 
T 400 2750 5 8 1 1 0 6 1
91 
pinnumber=T21
91 
pinnumber=T21
92 
T 200 2750 5 8 0 1 0 6 1
92 
T 400 2750 5 8 0 1 0 6 1
93 
pinseq=T21
93 
pinseq=T21
94 
}
94 
}
95 
P 4400 8400 4100 8400 1 0 0
95 
P 4800 8400 4300 8400 1 0 0
96 
{
96 
{
97 
T 4050 8400 9 10 1 1 0 7 1
97 
T 4250 8400 9 10 1 1 0 7 1
98 
pinlabel=RAM_D[05]
98 
pinlabel=RAM_D[05]
99 
T 4200 8450 5 8 1 1 0 0 1
99 
T 4400 8450 5 8 1 1 0 0 1
100 
pinnumber=R23
100 
pinnumber=R23
101 
T 4200 8450 5 8 0 1 0 0 1
101 
T 4400 8450 5 8 0 1 0 0 1
102 
pinseq=R23
102 
pinseq=R23
103 
}
103 
}
104 
P 4400 9900 4100 9900 1 0 0
104 
P 4800 9900 4300 9900 1 0 0
105 
{
105 
{
106 
T 4050 9900 9 10 1 1 0 7 1
106 
T 4250 9900 9 10 1 1 0 7 1
107 
pinlabel=RAM_D[00]
107 
pinlabel=RAM_D[00]
108 
T 4200 9950 5 8 1 1 0 0 1
108 
T 4400 9950 5 8 1 1 0 0 1
109 
pinnumber=T23
109 
pinnumber=T23
110 
T 4200 9950 5 8 0 1 0 0 1
110 
T 4400 9950 5 8 0 1 0 0 1
111 
pinseq=T23
111 
pinseq=T23
112 
}
112 
}
113 
P 0 6900 300 6900 1 0 0
113 
P 0 6900 500 6900 1 0 0
114 
{
114 
{
115 
T 350 6900 9 10 1 1 0 1 1
115 
T 550 6900 9 10 1 1 0 1 1
116 
pinlabel=RAM_A[10]
116 
pinlabel=RAM_A[10]
117 
T 200 6950 5 8 1 1 0 6 1
117 
T 400 6950 5 8 1 1 0 6 1
118 
pinnumber=Y22
118 
pinnumber=Y22
119 
T 200 6950 5 8 0 1 0 6 1
119 
T 400 6950 5 8 0 1 0 6 1
120 
pinseq=Y22
120 
pinseq=Y22
121 
}
121 
}
122 
P 0 4500 300 4500 1 0 0
122 
P 0 4500 500 4500 1 0 0
123 
{
123 
{
124 
T 350 4500 9 10 1 1 0 1 1
124 
T 550 4500 9 10 1 1 0 1 1
125 
pinlabel=RAM_DQM[2]
125 
pinlabel=RAM_DQM[2]
126 
T 200 4550 5 8 1 1 0 6 1
126 
T 400 4550 5 8 1 1 0 6 1
127 
pinnumber=V21
127 
pinnumber=V21
128 
T 200 4550 5 8 0 1 0 6 1
128 
T 400 4550 5 8 0 1 0 6 1
129 
pinseq=V21
129 
pinseq=V21
130 
}
130 
}
131 
P 4400 4200 4100 4200 1 0 0
131 
P 4800 4200 4300 4200 1 0 0
132 
{
132 
{
133 
T 4050 4200 9 10 1 1 0 7 1
133 
T 4250 4200 9 10 1 1 0 7 1
134 
pinlabel=RAM_D[19]
134 
pinlabel=RAM_D[19]
135 
T 4200 4250 5 8 1 1 0 0 1
135 
T 4400 4250 5 8 1 1 0 0 1
136 
pinnumber=H21
136 
pinnumber=H21
137 
T 4200 4250 5 8 0 1 0 0 1
137 
T 4400 4250 5 8 0 1 0 0 1
138 
pinseq=H21
138 
pinseq=H21
139 
}
139 
}
140 
P 4400 600 4100 600 1 0 0
140 
P 4800 600 4300 600 1 0 0
141 
{
141 
{
142 
T 4050 600 9 10 1 1 0 7 1
142 
T 4250 600 9 10 1 1 0 7 1
143 
pinlabel=RAM_D[31]
143 
pinlabel=RAM_D[31]
144 
T 4200 650 5 8 1 1 0 0 1
144 
T 4400 650 5 8 1 1 0 0 1
145 
pinnumber=E24
145 
pinnumber=E24
146 
T 4200 650 5 8 0 1 0 0 1
146 
T 4400 650 5 8 0 1 0 0 1
147 
pinseq=E24
147 
pinseq=E24
148 
}
148 
}
149 
P 4400 8700 4100 8700 1 0 0
149 
P 4800 8700 4300 8700 1 0 0
150 
{
150 
{
151 
T 4050 8700 9 10 1 1 0 7 1
151 
T 4250 8700 9 10 1 1 0 7 1
152 
pinlabel=RAM_D[04]
152 
pinlabel=RAM_D[04]
153 
T 4200 8750 5 8 1 1 0 0 1
153 
T 4400 8750 5 8 1 1 0 0 1
154 
pinnumber=P21
154 
pinnumber=P21
155 
T 4200 8750 5 8 0 1 0 0 1
155 
T 4400 8750 5 8 0 1 0 0 1
156 
pinseq=P21
156 
pinseq=P21
157 
}
157 
}
158 
P 4400 2400 4100 2400 1 0 0
158 
P 4800 2400 4300 2400 1 0 0
159 
{
159 
{
160 
T 4050 2400 9 10 1 1 0 7 1
160 
T 4250 2400 9 10 1 1 0 7 1
161 
pinlabel=RAM_D[25]
161 
pinlabel=RAM_D[25]
162 
T 4200 2450 5 8 1 1 0 0 1
162 
T 4400 2450 5 8 1 1 0 0 1
163 
pinnumber=J21
163 
pinnumber=J21
164 
T 4200 2450 5 8 0 1 0 0 1
164 
T 4400 2450 5 8 0 1 0 0 1
165 
pinseq=J21
165 
pinseq=J21
166 
}
166 
}
167 
P 0 3300 300 3300 1 0 0
167 
P 0 3300 500 3300 1 0 0
168 
{
168 
{
169 
T 350 3300 9 10 1 1 0 1 1
169 
T 550 3300 9 10 1 1 0 1 1
170 
pinlabel=RAM_RAS_N
170 
pinlabel=RAM_RAS_N
171 
T 200 3350 5 8 1 1 0 6 1
171 
T 400 3350 5 8 1 1 0 6 1
172 
pinnumber=U21
172 
pinnumber=U21
173 
T 200 3350 5 8 0 1 0 6 1
173 
T 400 3350 5 8 0 1 0 6 1
174 
pinseq=U21
174 
pinseq=U21
175 
}
175 
}
176 
P 0 6000 300 6000 1 0 0
176 
P 0 6000 500 6000 1 0 0
177 
{
177 
{
178 
T 350 6000 9 10 1 1 0 1 1
178 
T 550 6000 9 10 1 1 0 1 1
179 
pinlabel=RAM_A[13]
179 
pinlabel=RAM_A[13]
180 
T 200 6050 5 8 1 1 0 6 1
180 
T 400 6050 5 8 1 1 0 6 1
181 
pinnumber=AA24
181 
pinnumber=AA24
182 
T 200 6050 5 8 0 1 0 6 1
182 
T 400 6050 5 8 0 1 0 6 1
183 
pinseq=AA24
183 
pinseq=AA24
184 
}
184 
}
185 
P 4400 1200 4100 1200 1 0 0
185 
P 4800 1200 4300 1200 1 0 0
186 
{
186 
{
187 
T 4050 1200 9 10 1 1 0 7 1
187 
T 4250 1200 9 10 1 1 0 7 1
188 
pinlabel=RAM_D[29]
188 
pinlabel=RAM_D[29]
189 
T 4200 1250 5 8 1 1 0 0 1
189 
T 4400 1250 5 8 1 1 0 0 1
190 
pinnumber=F21
190 
pinnumber=F21
191 
T 4200 1250 5 8 0 1 0 0 1
191 
T 4400 1250 5 8 0 1 0 0 1
192 
pinseq=F21
192 
pinseq=F21
193 
}
193 
}
194 
P 0 2100 300 2100 1 0 0
194 
P 0 2100 500 2100 1 0 0
195 
{
195 
{
196 
T 350 2100 9 10 1 1 0 1 1
196 
T 550 2100 9 10 1 1 0 1 1
197 
pinlabel=RAM_CKE
197 
pinlabel=RAM_CKE
198 
T 200 2150 5 8 1 1 0 6 1
198 
T 400 2150 5 8 1 1 0 6 1
199 
pinnumber=U24
199 
pinnumber=U24
200 
T 200 2150 5 8 0 1 0 6 1
200 
T 400 2150 5 8 0 1 0 6 1
201 
pinseq=U24
201 
pinseq=U24
202 
}
202 
}
203 
P 0 2400 300 2400 1 0 0
203 
P 0 2400 500 2400 1 0 0
204 
{
204 
{
205 
T 350 2400 9 10 1 1 0 1 1
205 
T 550 2400 9 10 1 1 0 1 1
206 
pinlabel=RAM_CLK
206 
pinlabel=RAM_CLK
207 
T 200 2450 5 8 1 1 0 6 1
207 
T 400 2450 5 8 1 1 0 6 1
208 
pinnumber=U23
208 
pinnumber=U23
209 
T 200 2450 5 8 0 1 0 6 1
209 
T 400 2450 5 8 0 1 0 6 1
210 
pinseq=U23
210 
pinseq=U23
211 
}
211 
}
212 
P 0 9000 300 9000 1 0 0
212 
P 0 9000 500 9000 1 0 0
213 
{
213 
{
214 
T 350 9000 9 10 1 1 0 1 1
214 
T 550 9000 9 10 1 1 0 1 1
215 
pinlabel=RAM_A[03]
215 
pinlabel=RAM_A[03]
216 
T 200 9050 5 8 1 1 0 6 1
216 
T 400 9050 5 8 1 1 0 6 1
217 
pinnumber=AD24
217 
pinnumber=AD24
218 
T 200 9050 5 8 0 1 0 6 1
218 
T 400 9050 5 8 0 1 0 6 1
219 
pinseq=AD24
219 
pinseq=AD24
220 
}
220 
}
221 
P 0 8700 300 8700 1 0 0
221 
P 0 8700 500 8700 1 0 0
222 
{
222 
{
223 
T 350 8700 9 10 1 1 0 1 1
223 
T 550 8700 9 10 1 1 0 1 1
224 
pinlabel=RAM_A[04]
224 
pinlabel=RAM_A[04]
225 
T 200 8750 5 8 1 1 0 6 1
225 
T 400 8750 5 8 1 1 0 6 1
226 
pinnumber=AC22
226 
pinnumber=AC22
227 
T 200 8750 5 8 0 1 0 6 1
227 
T 400 8750 5 8 0 1 0 6 1
228 
pinseq=AC22
228 
pinseq=AC22
229 
}
229 
}
230 
P 4400 2700 4100 2700 1 0 0
230 
P 4800 2700 4300 2700 1 0 0
231 
{
231 
{
232 
T 4050 2700 9 10 1 1 0 7 1
232 
T 4250 2700 9 10 1 1 0 7 1
233 
pinlabel=RAM_D[24]
233 
pinlabel=RAM_D[24]
234 
T 4200 2750 5 8 1 1 0 0 1
234 
T 4400 2750 5 8 1 1 0 0 1
235 
pinnumber=G23
235 
pinnumber=G23
236 
T 4200 2750 5 8 0 1 0 0 1
236 
T 4400 2750 5 8 0 1 0 0 1
237 
pinseq=G23
237 
pinseq=G23
238 
}
238 
}
239 
P 4400 5400 4100 5400 1 0 0
239 
P 4800 5400 4300 5400 1 0 0
240 
{
240 
{
241 
T 4050 5400 9 10 1 1 0 7 1
241 
T 4250 5400 9 10 1 1 0 7 1
242 
pinlabel=RAM_D[15]
242 
pinlabel=RAM_D[15]
243 
T 4200 5450 5 8 1 1 0 0 1
243 
T 4400 5450 5 8 1 1 0 0 1
244 
pinnumber=L24
244 
pinnumber=L24
245 
T 4200 5450 5 8 0 1 0 0 1
245 
T 4400 5450 5 8 0 1 0 0 1
246 
pinseq=L24
246 
pinseq=L24
247 
}
247 
}
248 
P 0 4200 300 4200 1 0 0
248 
P 0 4200 500 4200 1 0 0
249 
{
249 
{
250 
T 350 4200 9 10 1 1 0 1 1
250 
T 550 4200 9 10 1 1 0 1 1
251 
pinlabel=RAM_DQM[3]
251 
pinlabel=RAM_DQM[3]
252 
T 200 4250 5 8 1 1 0 6 1
252 
T 400 4250 5 8 1 1 0 6 1
253 
pinnumber=W24
253 
pinnumber=W24
254 
T 200 4250 5 8 0 1 0 6 1
254 
T 400 4250 5 8 0 1 0 6 1
255 
pinseq=W24
255 
pinseq=W24
256 
}
256 
}
257 
P 4400 900 4100 900 1 0 0
257 
P 4800 900 4300 900 1 0 0
258 
{
258 
{
259 
T 4050 900 9 10 1 1 0 7 1
259 
T 4250 900 9 10 1 1 0 7 1
260 
pinlabel=RAM_D[30]
260 
pinlabel=RAM_D[30]
261 
T 4200 950 5 8 1 1 0 0 1
261 
T 4400 950 5 8 1 1 0 0 1
262 
pinnumber=E23
262 
pinnumber=E23
263 
T 4200 950 5 8 0 1 0 0 1
263 
T 4400 950 5 8 0 1 0 0 1
264 
pinseq=E23
264 
pinseq=E23
265 
}
265 
}
266 
P 4400 7800 4100 7800 1 0 0
266 
P 4800 7800 4300 7800 1 0 0
267 
{
267 
{
268 
T 4050 7800 9 10 1 1 0 7 1
268 
T 4250 7800 9 10 1 1 0 7 1
269 
pinlabel=RAM_D[08]
269 
pinlabel=RAM_D[08]
270 
T 4200 7850 5 8 1 1 0 0 1
270 
T 4400 7850 5 8 1 1 0 0 1
271 
pinnumber=P23
271 
pinnumber=P23
272 
T 4200 7850 5 8 0 1 0 0 1
272 
T 4400 7850 5 8 0 1 0 0 1
273 
pinseq=P23
273 
pinseq=P23
274 
}
274 
}
275 
P 0 7800 300 7800 1 0 0
275 
P 0 7800 500 7800 1 0 0
276 
{
276 
{
277 
T 350 7800 9 10 1 1 0 1 1
277 
T 550 7800 9 10 1 1 0 1 1
278 
pinlabel=RAM_A[07]
278 
pinlabel=RAM_A[07]
279 
T 200 7850 5 8 1 1 0 6 1
279 
T 400 7850 5 8 1 1 0 6 1
280 
pinnumber=AB22
280 
pinnumber=AB22
281 
T 200 7850 5 8 0 1 0 6 1
281 
T 400 7850 5 8 0 1 0 6 1
282 
pinseq=AB22
282 
pinseq=AB22
283 
}
283 
}
284 
P 4400 6000 4100 6000 1 0 0
284 
P 4800 6000 4300 6000 1 0 0
285 
{
285 
{
286 
T 4050 6000 9 10 1 1 0 7 1
286 
T 4250 6000 9 10 1 1 0 7 1
287 
pinlabel=RAM_D[13]
287 
pinlabel=RAM_D[13]
288 
T 4200 6050 5 8 1 1 0 0 1
288 
T 4400 6050 5 8 1 1 0 0 1
289 
pinnumber=L22
289 
pinnumber=L22
290 
T 4200 6050 5 8 0 1 0 0 1
290 
T 4400 6050 5 8 0 1 0 0 1
291 
pinseq=L22
291 
pinseq=L22
292 
}
292 
}
293 
P 4400 7500 4100 7500 1 0 0
293 
P 4800 7500 4300 7500 1 0 0
294 
{
294 
{
295 
T 4050 7500 9 10 1 1 0 7 1
295 
T 4250 7500 9 10 1 1 0 7 1
296 
pinlabel=RAM_D[07]
296 
pinlabel=RAM_D[07]
297 
T 4200 7550 5 8 1 1 0 0 1
297 
T 4400 7550 5 8 1 1 0 0 1
298 
pinnumber=N21
298 
pinnumber=N21
299 
T 4200 7550 5 8 0 1 0 0 1
299 
T 4400 7550 5 8 0 1 0 0 1
300 
pinseq=N21
300 
pinseq=N21
301 
}
301 
}
302 
P 4400 9300 4100 9300 1 0 0
302 
P 4800 9300 4300 9300 1 0 0
303 
{
303 
{
304 
T 4050 9300 9 10 1 1 0 7 1
304 
T 4250 9300 9 10 1 1 0 7 1
305 
pinlabel=RAM_D[02]
305 
pinlabel=RAM_D[02]
306 
T 4200 9350 5 8 1 1 0 0 1
306 
T 4400 9350 5 8 1 1 0 0 1
307 
pinnumber=T24
307 
pinnumber=T24
308 
T 4200 9350 5 8 0 1 0 0 1
308 
T 4400 9350 5 8 0 1 0 0 1
309 
pinseq=T24
309 
pinseq=T24
310 
}
310 
}
311 
P 0 5100 300 5100 1 0 0
311 
P 0 5100 500 5100 1 0 0
312 
{
312 
{
313 
T 350 5100 9 10 1 1 0 1 1
313 
T 550 5100 9 10 1 1 0 1 1
314 
pinlabel=RAM_DQM[0]
314 
pinlabel=RAM_DQM[0]
315 
T 200 5150 5 8 1 1 0 6 1
315 
T 400 5150 5 8 1 1 0 6 1
316 
pinnumber=Y24
316 
pinnumber=Y24
317 
T 200 5150 5 8 0 1 0 6 1
317 
T 400 5150 5 8 0 1 0 6 1
318 
pinseq=Y24
318 
pinseq=Y24
319 
}
319 
}
320 
P 0 5700 300 5700 1 0 0
320 
P 0 5700 500 5700 1 0 0
321 
{
321 
{
322 
T 350 5700 9 10 1 1 0 1 1
322 
T 550 5700 9 10 1 1 0 1 1
323 
pinlabel=RAM_A[14]
323 
pinlabel=RAM_A[14]
324 
T 200 5750 5 8 1 1 0 6 1
324 
T 400 5750 5 8 1 1 0 6 1
325 
pinnumber=W21
325 
pinnumber=W21
326 
T 200 5750 5 8 0 1 0 6 1
326 
T 400 5750 5 8 0 1 0 6 1
327 
pinseq=W21
327 
pinseq=W21
328 
}
328 
}
329 
P 4400 6300 4100 6300 1 0 0
329 
P 4800 6300 4300 6300 1 0 0
330 
{
330 
{
331 
T 4050 6300 9 10 1 1 0 7 1
331 
T 4250 6300 9 10 1 1 0 7 1
332 
pinlabel=RAM_D[12]
332 
pinlabel=RAM_D[12]
333 
T 4200 6350 5 8 1 1 0 0 1
333 
T 4400 6350 5 8 1 1 0 0 1
334 
pinnumber=M24
334 
pinnumber=M24
335 
T 4200 6350 5 8 0 1 0 0 1
335 
T 4400 6350 5 8 0 1 0 0 1
336 
pinseq=M24
336 
pinseq=M24
337 
}
337 
}
338 
P 4400 1800 4100 1800 1 0 0
338 
P 4800 1800 4300 1800 1 0 0
339 
{
339 
{
340 
T 4050 1800 9 10 1 1 0 7 1
340 
T 4250 1800 9 10 1 1 0 7 1
341 
pinlabel=RAM_D[27]
341 
pinlabel=RAM_D[27]
342 
T 4200 1850 5 8 1 1 0 0 1
342 
T 4400 1850 5 8 1 1 0 0 1
343 
pinnumber=G24
343 
pinnumber=G24
344 
T 4200 1850 5 8 0 1 0 0 1
344 
T 4400 1850 5 8 0 1 0 0 1
345 
pinseq=G24
345 
pinseq=G24
346 
}
346 
}
347 
P 0 8400 300 8400 1 0 0
347 
P 0 8400 500 8400 1 0 0
348 
{
348 
{
349 
T 350 8400 9 10 1 1 0 1 1
349 
T 550 8400 9 10 1 1 0 1 1
350 
pinlabel=RAM_A[05]
350 
pinlabel=RAM_A[05]
351 
T 200 8450 5 8 1 1 0 6 1
351 
T 400 8450 5 8 1 1 0 6 1
352 
pinnumber=AA21
352 
pinnumber=AA21
353 
T 200 8450 5 8 0 1 0 6 1
353 
T 400 8450 5 8 0 1 0 6 1
354 
pinseq=AA21
354 
pinseq=AA21
355 
}
355 
}
356 
P 4400 5100 4100 5100 1 0 0
356 
P 4800 5100 4300 5100 1 0 0
357 
{
357 
{
358 
T 4050 5100 9 10 1 1 0 7 1
358 
T 4250 5100 9 10 1 1 0 7 1
359 
pinlabel=RAM_D[16]/DDR_DQS0
359 
pinlabel=RAM_D[16]/DDR_DQS0
360 
T 4200 5150 5 8 1 1 0 0 1
360 
T 4400 5150 5 8 1 1 0 0 1
361 
pinnumber=L23
361 
pinnumber=L23
362 
T 4200 5150 5 8 0 1 0 0 1
362 
T 4400 5150 5 8 0 1 0 0 1
363 
pinseq=L23
363 
pinseq=L23
364 
}
364 
}
365 
P 4400 9000 4100 9000 1 0 0
365 
P 4800 9000 4300 9000 1 0 0
366 
{
366 
{
367 
T 4050 9000 9 10 1 1 0 7 1
367 
T 4250 9000 9 10 1 1 0 7 1
368 
pinlabel=RAM_D[03]
368 
pinlabel=RAM_D[03]
369 
T 4200 9050 5 8 1 1 0 0 1
369 
T 4400 9050 5 8 1 1 0 0 1
370 
pinnumber=R24
370 
pinnumber=R24
371 
T 4200 9050 5 8 0 1 0 0 1
371 
T 4400 9050 5 8 0 1 0 0 1
372 
pinseq=R24
372 
pinseq=R24
373 
}
373 
}
374 
P 0 9600 300 9600 1 0 0
374 
P 0 9600 500 9600 1 0 0
375 
{
375 
{
376 
T 350 9600 9 10 1 1 0 1 1
376 
T 550 9600 9 10 1 1 0 1 1
377 
pinlabel=RAM_A[01]
377 
pinlabel=RAM_A[01]
378 
T 200 9650 5 8 1 1 0 6 1
378 
T 400 9650 5 8 1 1 0 6 1
379 
pinnumber=AB20
379 
pinnumber=AB20
380 
T 200 9650 5 8 0 1 0 6 1
380 
T 400 9650 5 8 0 1 0 6 1
381 
pinseq=AB20
381 
pinseq=AB20
382 
}
382 
}
383 
P 4400 1500 4100 1500 1 0 0
383 
P 4800 1500 4300 1500 1 0 0
384 
{
384 
{
385 
T 4050 1500 9 10 1 1 0 7 1
385 
T 4250 1500 9 10 1 1 0 7 1
386 
pinlabel=RAM_D[28]
386 
pinlabel=RAM_D[28]
387 
T 4200 1550 5 8 1 1 0 0 1
387 
T 4400 1550 5 8 1 1 0 0 1
388 
pinnumber=F24
388 
pinnumber=F24
389 
T 4200 1550 5 8 0 1 0 0 1
389 
T 4400 1550 5 8 0 1 0 0 1
390 
pinseq=F24
390 
pinseq=F24
391 
}
391 
}
392 
P 0 8100 300 8100 1 0 0
392 
P 0 8100 500 8100 1 0 0
393 
{
393 
{
394 
T 350 8100 9 10 1 1 0 1 1
394 
T 550 8100 9 10 1 1 0 1 1
395 
pinlabel=RAM_A[06]
395 
pinlabel=RAM_A[06]
396 
T 200 8150 5 8 1 1 0 6 1
396 
T 400 8150 5 8 1 1 0 6 1
397 
pinnumber=AC23
397 
pinnumber=AC23
398 
T 200 8150 5 8 0 1 0 6 1
398 
T 400 8150 5 8 0 1 0 6 1
399 
pinseq=AC23
399 
pinseq=AC23
400 
}
400 
}
401 
P 4400 6600 4100 6600 1 0 0
401 
P 4800 6600 4300 6600 1 0 0
402 
{
402 
{
403 
T 4050 6600 9 10 1 1 0 7 1
403 
T 4250 6600 9 10 1 1 0 7 1
404 
pinlabel=RAM_D[11]
404 
pinlabel=RAM_D[11]
405 
T 4200 6650 5 8 1 1 0 0 1
405 
T 4400 6650 5 8 1 1 0 0 1
406 
pinnumber=N23
406 
pinnumber=N23
407 
T 4200 6650 5 8 0 1 0 0 1
407 
T 4400 6650 5 8 0 1 0 0 1
408 
pinseq=N23
408 
pinseq=N23
409 
}
409 
}
410 
P 4400 7200 4100 7200 1 0 0
410 
P 4800 7200 4300 7200 1 0 0
411 
{
411 
{
412 
T 4050 7200 9 10 1 1 0 7 1
412 
T 4250 7200 9 10 1 1 0 7 1
413 
pinlabel=RAM_D[09]
413 
pinlabel=RAM_D[09]
414 
T 4200 7250 5 8 1 1 0 0 1
414 
T 4400 7250 5 8 1 1 0 0 1
415 
pinnumber=N24
415 
pinnumber=N24
416 
T 4200 7250 5 8 0 1 0 0 1
416 
T 4400 7250 5 8 0 1 0 0 1
417 
pinseq=N24
417 
pinseq=N24
418 
}
418 
}
419 
P 0 9300 300 9300 1 0 0
419 
P 0 9300 500 9300 1 0 0
420 
{
420 
{
421 
T 350 9300 9 10 1 1 0 1 1
421 
T 550 9300 9 10 1 1 0 1 1
422 
pinlabel=RAM_A[02]
422 
pinlabel=RAM_A[02]
423 
T 200 9350 5 8 1 1 0 6 1
423 
T 400 9350 5 8 1 1 0 6 1
424 
pinnumber=AD23
424 
pinnumber=AD23
425 
T 200 9350 5 8 0 1 0 6 1
425 
T 400 9350 5 8 0 1 0 6 1
426 
pinseq=AD23
426 
pinseq=AD23
427 
}
427 
}
428 
P 0 4800 300 4800 1 0 0
428 
P 0 4800 500 4800 1 0 0
429 
{
429 
{
430 
T 350 4800 9 10 1 1 0 1 1
430 
T 550 4800 9 10 1 1 0 1 1
431 
pinlabel=RAM_DQM[1]
431 
pinlabel=RAM_DQM[1]
432 
T 200 4850 5 8 1 1 0 6 1
432 
T 400 4850 5 8 1 1 0 6 1
433 
pinnumber=W23
433 
pinnumber=W23
434 
T 200 4850 5 8 0 1 0 6 1
434 
T 400 4850 5 8 0 1 0 6 1
435 
pinseq=W23
435 
pinseq=W23
436 
}
436 
}
437 
P 4400 6900 4100 6900 1 0 0
437 
P 4800 6900 4300 6900 1 0 0
438 
{
438 
{
439 
T 4050 6900 9 10 1 1 0 7 1
439 
T 4250 6900 9 10 1 1 0 7 1
440 
pinlabel=RAM_D[10]
440 
pinlabel=RAM_D[10]
441 
T 4200 6950 5 8 1 1 0 0 1
441 
T 4400 6950 5 8 1 1 0 0 1
442 
pinnumber=M22
442 
pinnumber=M22
443 
T 4200 6950 5 8 0 1 0 0 1
443 
T 4400 6950 5 8 0 1 0 0 1
444 
pinseq=M22
444 
pinseq=M22
445 
}
445 
}
446 
P 4400 4500 4100 4500 1 0 0
446 
P 4800 4500 4300 4500 1 0 0
447 
{
447 
{
448 
T 4050 4500 9 10 1 1 0 7 1
448 
T 4250 4500 9 10 1 1 0 7 1
449 
pinlabel=RAM_D[18]/DDR_NCLK
449 
pinlabel=RAM_D[18]/DDR_NCLK
450 
T 4200 4550 5 8 1 1 0 0 1
450 
T 4400 4550 5 8 1 1 0 0 1
451 
pinnumber=K24
451 
pinnumber=K24
452 
T 4200 4550 5 8 0 1 0 0 1
452 
T 4400 4550 5 8 0 1 0 0 1
453 
pinseq=K24
453 
pinseq=K24
454 
}
454 
}
455 
P 4400 3900 4100 3900 1 0 0
455 
P 4800 3900 4300 3900 1 0 0
456 
{
456 
{
457 
T 4050 3900 9 10 1 1 0 7 1
457 
T 4250 3900 9 10 1 1 0 7 1
458 
pinlabel=RAM_D[20]
458 
pinlabel=RAM_D[20]
459 
T 4200 3950 5 8 1 1 0 0 1
459 
T 4400 3950 5 8 1 1 0 0 1
460 
pinnumber=J24
460 
pinnumber=J24
461 
T 4200 3950 5 8 0 1 0 0 1
461 
T 4400 3950 5 8 0 1 0 0 1
462 
pinseq=J24
462 
pinseq=J24
463 
}
463 
}
464 
P 0 7500 300 7500 1 0 0
464 
P 0 7500 500 7500 1 0 0
465 
{
465 
{
466 
T 350 7500 9 10 1 1 0 1 1
466 
T 550 7500 9 10 1 1 0 1 1
467 
pinlabel=RAM_A[08]
467 
pinlabel=RAM_A[08]
468 
T 200 7550 5 8 1 1 0 6 1
468 
T 400 7550 5 8 1 1 0 6 1
469 
pinnumber=AB23
469 
pinnumber=AB23
470 
T 200 7550 5 8 0 1 0 6 1
470 
T 400 7550 5 8 0 1 0 6 1
471 
pinseq=AB23
471 
pinseq=AB23
472 
}
472 
}
473 
P 0 6600 300 6600 1 0 0
473 
P 0 6600 500 6600 1 0 0
474 
{
474 
{
475 
T 350 6600 9 10 1 1 0 1 1
475 
T 550 6600 9 10 1 1 0 1 1
476 
pinlabel=RAM_A[11]
476 
pinlabel=RAM_A[11]
477 
T 200 6650 5 8 1 1 0 6 1
477 
T 400 6650 5 8 1 1 0 6 1
478 
pinnumber=AB24
478 
pinnumber=AB24
479 
T 200 6650 5 8 0 1 0 6 1
479 
T 400 6650 5 8 0 1 0 6 1
480 
pinseq=AB24
480 
pinseq=AB24
481 
}
481 
}
482 
P 4400 3000 4100 3000 1 0 0
482 
P 4800 3000 4300 3000 1 0 0
483 
{
483 
{
484 
T 4050 3000 9 10 1 1 0 7 1
484 
T 4250 3000 9 10 1 1 0 7 1
485 
pinlabel=RAM_D[23]
485 
pinlabel=RAM_D[23]
486 
T 4200 3050 5 8 1 1 0 0 1
486 
T 4400 3050 5 8 1 1 0 0 1
487 
pinnumber=H22
487 
pinnumber=H22
488 
T 4200 3050 5 8 0 1 0 0 1
488 
T 4400 3050 5 8 0 1 0 0 1
489 
pinseq=H22
489 
pinseq=H22
490 
}
490 
}
491 
P 0 1200 300 1200 1 0 0
491 
P 0 1200 500 1200 1 0 0
492 
{
492 
{
493 
T 350 1200 9 10 1 1 0 1 1
493 
T 550 1200 9 10 1 1 0 1 1
494 
pinlabel=RAM_CS_N
494 
pinlabel=RAM_CS_N
495 
T 200 1250 5 8 1 1 0 6 1
495 
T 400 1250 5 8 1 1 0 6 1
496 
pinnumber=V24
496 
pinnumber=V24
497 
T 200 1250 5 8 0 1 0 6 1
497 
T 400 1250 5 8 0 1 0 6 1
498 
pinseq=V24
498 
pinseq=V24
499 
}
499 
}
500 
P 4400 4800 4100 4800 1 0 0
500 
P 4800 4800 4300 4800 1 0 0
501 
{
501 
{
502 
T 4050 4800 9 10 1 1 0 7 1
502 
T 4250 4800 9 10 1 1 0 7 1
503 
pinlabel=RAM_D[17]/DDR_DQS1
503 
pinlabel=RAM_D[17]/DDR_DQS1
504 
T 4200 4850 5 8 1 1 0 0 1
504 
T 4400 4850 5 8 1 1 0 0 1
505 
pinnumber=L21
505 
pinnumber=L21
506 
T 4200 4850 5 8 0 1 0 0 1
506 
T 4400 4850 5 8 0 1 0 0 1
507 
pinseq=L21
507 
pinseq=L21
508 
}
508 
}
509 
P 4400 8100 4100 8100 1 0 0
509 
P 4800 8100 4300 8100 1 0 0
510 
{
510 
{
511 
T 4050 8100 9 10 1 1 0 7 1
511 
T 4250 8100 9 10 1 1 0 7 1
512 
pinlabel=RAM_D[06]
512 
pinlabel=RAM_D[06]
513 
T 4200 8150 5 8 1 1 0 0 1
513 
T 4400 8150 5 8 1 1 0 0 1
514 
pinnumber=P24
514 
pinnumber=P24
515 
T 4200 8150 5 8 0 1 0 0 1
515 
T 4400 8150 5 8 0 1 0 0 1
516 
pinseq=P24
516 
pinseq=P24
517 
}
517 
}
518 
P 4400 9600 4100 9600 1 0 0
518 
P 4800 9600 4300 9600 1 0 0
519 
{
519 
{
520 
T 4050 9600 9 10 1 1 0 7 1
520 
T 4250 9600 9 10 1 1 0 7 1
521 
pinlabel=RAM_D[01]
521 
pinlabel=RAM_D[01]
522 
T 4200 9650 5 8 1 1 0 0 1
522 
T 4400 9650 5 8 1 1 0 0 1
523 
pinnumber=T22
523 
pinnumber=T22
524 
T 4200 9650 5 8 0 1 0 0 1
524 
T 4400 9650 5 8 0 1 0 0 1
525 
pinseq=T22
525 
pinseq=T22
526 
}
526 
}
527 
P 4400 3300 4100 3300 1 0 0
527 
P 4800 3300 4300 3300 1 0 0
528 
{
528 
{
529 
T 4050 3300 9 10 1 1 0 7 1
529 
T 4250 3300 9 10 1 1 0 7 1
530 
pinlabel=RAM_D[22]
530 
pinlabel=RAM_D[22]
531 
T 4200 3350 5 8 1 1 0 0 1
531 
T 4400 3350 5 8 1 1 0 0 1
532 
pinnumber=K23
532 
pinnumber=K23
533 
T 4200 3350 5 8 0 1 0 0 1
533 
T 4400 3350 5 8 0 1 0 0 1
534 
pinseq=K23
534 
pinseq=K23
535 
}
535 
}
536 
P 0 1500 300 1500 1 0 0
536 
P 0 1500 500 1500 1 0 0
537 
{
537 
{
538 
T 350 1500 9 10 1 1 0 1 1
538 
T 550 1500 9 10 1 1 0 1 1
539 
pinlabel=RAM_WR_N
539 
pinlabel=RAM_WR_N
540 
T 200 1550 5 8 1 1 0 6 1
540 
T 400 1550 5 8 1 1 0 6 1
541 
pinnumber=V22
541 
pinnumber=V22
542 
T 200 1550 5 8 0 1 0 6 1
542 
T 400 1550 5 8 0 1 0 6 1
543 
pinseq=V22
543 
pinseq=V22
544 
}
544 
}