Rev 138 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
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| Line 1... | Line 1... | ||
| 1 | v 20060123 1 |
1 | v 20060123 1 |
| 2 | B 300 300 3900 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
2 | B 500 300 3900 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
| 3 | T 4200 2800 9 10 0 0 0 0 1 |
3 | T 4200 2800 9 10 0 0 0 0 1 |
| 4 | uselicense=unlimited |
4 | uselicense=unlimited |
| 5 | T 4200 3000 9 10 0 0 0 0 1 |
5 | T 4200 3000 9 10 0 0 0 0 1 |
| 6 | distlicense=GPL (v2 or any later version) |
6 | distlicense=GPL (v2 or any later version) |
| 7 | T 4200 3200 9 10 0 0 0 0 1 |
7 | T 4200 3200 9 10 0 0 0 0 1 |
| Line 10... | Line 10... | ||
| 10 | author=Tibor Palinkas |
10 | author=Tibor Palinkas |
| 11 | T 4200 3600 9 10 0 0 0 0 1 |
11 | T 4200 3600 9 10 0 0 0 0 1 |
| 12 | description=NXP 16/32-bit ARM926EJ-S microcontroller |
12 | description=NXP 16/32-bit ARM926EJ-S microcontroller |
| 13 | T 4200 3800 9 10 0 0 0 0 1 |
13 | T 4200 3800 9 10 0 0 0 0 1 |
| 14 | documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf |
14 | documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf |
| 15 | T 300 2800 5 10 1 1 0 0 1 |
15 | T 4400 2800 5 10 1 1 0 6 1 |
| 16 | block=VDD (CORE) |
16 | block=VDD (CORE) |
| 17 | T 300 3000 5 10 1 1 0 0 1 |
17 | T 500 2800 5 10 1 1 0 0 1 |
| 18 | device=LPC3180FEL320 |
18 | device=LPC3180FEL320 |
| 19 | T 300 3200 5 10 1 1 0 0 1 |
19 | T 500 3000 5 10 1 1 0 0 1 |
| 20 | footprint=SOT824 |
20 | footprint=SOT824 |
| 21 | T 300 3400 5 10 1 1 0 0 1 |
21 | T 500 3200 5 10 1 1 0 0 1 |
| 22 | refdes=U? |
22 | refdes=U? |
| 23 | P 4500 2100 4200 2100 1 0 0 |
23 | P 4900 2100 4400 2100 1 0 0 |
| 24 | {
|
24 | {
|
| 25 | T 4150 2100 9 10 1 1 0 7 1 |
25 | T 4350 2100 9 10 1 1 0 7 1 |
| 26 | pinlabel=VDD_COREFXD12_02 |
26 | pinlabel=VDD_COREFXD12_02 |
| 27 | T 4300 2150 5 8 1 1 0 0 1 |
27 | T 4500 2150 5 8 1 1 0 0 1 |
| 28 | pinnumber=D18 |
28 | pinnumber=D18 |
| 29 | T 4300 2150 5 8 0 1 0 0 1 |
29 | T 4500 2150 5 8 0 1 0 0 1 |
| 30 | pinseq=D18 |
30 | pinseq=D18 |
| 31 | } |
31 | } |
| 32 | P 0 2100 300 2100 1 0 0 |
32 | P 0 2100 500 2100 1 0 0 |
| 33 | {
|
33 | {
|
| 34 | T 350 2100 9 10 1 1 0 1 1 |
34 | T 550 2100 9 10 1 1 0 1 1 |
| 35 | pinlabel=VDD_CORE12_02 |
35 | pinlabel=VDD_CORE12_02 |
| 36 | T 200 2150 5 8 1 1 0 6 1 |
36 | T 400 2150 5 8 1 1 0 6 1 |
| 37 | pinnumber=D6 |
37 | pinnumber=D6 |
| 38 | T 200 2150 5 8 0 1 0 6 1 |
38 | T 400 2150 5 8 0 1 0 6 1 |
| 39 | pinseq=D6 |
39 | pinseq=D6 |
| 40 | } |
40 | } |
| 41 | P 0 1800 300 1800 1 0 0 |
41 | P 0 1800 500 1800 1 0 0 |
| 42 | {
|
42 | {
|
| 43 | T 350 1800 9 10 1 1 0 1 1 |
43 | T 550 1800 9 10 1 1 0 1 1 |
| 44 | pinlabel=VDD_CORE12_03 |
44 | pinlabel=VDD_CORE12_03 |
| 45 | T 200 1850 5 8 1 1 0 6 1 |
45 | T 400 1850 5 8 1 1 0 6 1 |
| 46 | pinnumber=K21 |
46 | pinnumber=K21 |
| 47 | T 200 1850 5 8 0 1 0 6 1 |
47 | T 400 1850 5 8 0 1 0 6 1 |
| 48 | pinseq=K21 |
48 | pinseq=K21 |
| 49 | } |
49 | } |
| 50 | P 0 600 300 600 1 0 0 |
50 | P 0 600 500 600 1 0 0 |
| 51 | {
|
51 | {
|
| 52 | T 350 600 9 10 1 1 0 1 1 |
52 | T 550 600 9 10 1 1 0 1 1 |
| 53 | pinlabel=VDD_CORE12_08 |
53 | pinlabel=VDD_CORE12_08 |
| 54 | T 200 650 5 8 1 1 0 6 1 |
54 | T 400 650 5 8 1 1 0 6 1 |
| 55 | pinnumber=AB18 |
55 | pinnumber=AB18 |
| 56 | T 200 650 5 8 0 1 0 6 1 |
56 | T 400 650 5 8 0 1 0 6 1 |
| 57 | pinseq=AB18 |
57 | pinseq=AB18 |
| 58 | } |
58 | } |
| 59 | P 4500 2400 4200 2400 1 0 0 |
59 | P 4900 2400 4400 2400 1 0 0 |
| 60 | {
|
60 | {
|
| 61 | T 4150 2400 9 10 1 1 0 7 1 |
61 | T 4350 2400 9 10 1 1 0 7 1 |
| 62 | pinlabel=VDD_COREFXD12_01 |
62 | pinlabel=VDD_COREFXD12_01 |
| 63 | T 4300 2450 5 8 1 1 0 0 1 |
63 | T 4500 2450 5 8 1 1 0 0 1 |
| 64 | pinnumber=C10 |
64 | pinnumber=C10 |
| 65 | T 4300 2450 5 8 0 1 0 0 1 |
65 | T 4500 2450 5 8 0 1 0 0 1 |
| 66 | pinseq=C10 |
66 | pinseq=C10 |
| 67 | } |
67 | } |
| 68 | P 0 1500 300 1500 1 0 0 |
68 | P 0 1500 500 1500 1 0 0 |
| 69 | {
|
69 | {
|
| 70 | T 350 1500 9 10 1 1 0 1 1 |
70 | T 550 1500 9 10 1 1 0 1 1 |
| 71 | pinlabel=VDD_CORE12_05 |
71 | pinlabel=VDD_CORE12_05 |
| 72 | T 200 1550 5 8 1 1 0 6 1 |
72 | T 400 1550 5 8 1 1 0 6 1 |
| 73 | pinnumber=L3 |
73 | pinnumber=L3 |
| 74 | T 200 1550 5 8 0 1 0 6 1 |
74 | T 400 1550 5 8 0 1 0 6 1 |
| 75 | pinseq=L3 |
75 | pinseq=L3 |
| 76 | } |
76 | } |
| 77 | P 0 900 300 900 1 0 0 |
77 | P 0 900 500 900 1 0 0 |
| 78 | {
|
78 | {
|
| 79 | T 350 900 9 10 1 1 0 1 1 |
79 | T 550 900 9 10 1 1 0 1 1 |
| 80 | pinlabel=VDD_CORE12_07 |
80 | pinlabel=VDD_CORE12_07 |
| 81 | T 200 950 5 8 1 1 0 6 1 |
81 | T 400 950 5 8 1 1 0 6 1 |
| 82 | pinnumber=AB6 |
82 | pinnumber=AB6 |
| 83 | T 200 950 5 8 0 1 0 6 1 |
83 | T 400 950 5 8 0 1 0 6 1 |
| 84 | pinseq=AB6 |
84 | pinseq=AB6 |
| 85 | } |
85 | } |
| 86 | P 0 1200 300 1200 1 0 0 |
86 | P 0 1200 500 1200 1 0 0 |
| 87 | {
|
87 | {
|
| 88 | T 350 1200 9 10 1 1 0 1 1 |
88 | T 550 1200 9 10 1 1 0 1 1 |
| 89 | pinlabel=VDD_CORE12_06 |
89 | pinlabel=VDD_CORE12_06 |
| 90 | T 200 1250 5 8 1 1 0 6 1 |
90 | T 400 1250 5 8 1 1 0 6 1 |
| 91 | pinnumber=AA12 |
91 | pinnumber=AA12 |
| 92 | T 200 1250 5 8 0 1 0 6 1 |
92 | T 400 1250 5 8 0 1 0 6 1 |
| 93 | pinseq=AA12 |
93 | pinseq=AA12 |
| 94 | } |
94 | } |
| 95 | P 0 2400 300 2400 1 0 0 |
95 | P 0 2400 500 2400 1 0 0 |
| 96 | {
|
96 | {
|
| 97 | T 350 2400 9 10 1 1 0 1 1 |
97 | T 550 2400 9 10 1 1 0 1 1 |
| 98 | pinlabel=VDD_CORE12_01 |
98 | pinlabel=VDD_CORE12_01 |
| 99 | T 200 2450 5 8 1 1 0 6 1 |
99 | T 400 2450 5 8 1 1 0 6 1 |
| 100 | pinnumber=AA2 |
100 | pinnumber=AA2 |
| 101 | T 200 2450 5 8 0 1 0 6 1 |
101 | T 400 2450 5 8 0 1 0 6 1 |
| 102 | pinseq=AA2 |
102 | pinseq=AA2 |
| 103 | } |
103 | } |