Rev 146 | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
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1 | v 20060123 1 |
1 | v 20060123 1 |
2 | B 500 300 2100 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
2 | B 500 300 2900 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
3 | T 2400 2800 9 10 0 0 0 0 1 |
3 | T 3200 2800 9 10 0 0 0 0 1 |
4 | uselicense=unlimited |
4 | uselicense=unlimited |
5 | T 2400 3000 9 10 0 0 0 0 1 |
5 | T 3200 3000 9 10 0 0 0 0 1 |
6 | distlicense=GPL (v2 or any later version) |
6 | distlicense=GPL (v2 or any later version) |
7 | T 2400 3200 9 10 0 0 0 0 1 |
7 | T 3200 3200 9 10 0 0 0 0 1 |
8 | copyright=2008 Tibor Palinkas |
8 | copyright=2008 Tibor Palinkas |
9 | T 2400 3400 9 10 0 0 0 0 1 |
9 | T 3200 3400 9 10 0 0 0 0 1 |
10 | author=Tibor Palinkas |
10 | author=Tibor Palinkas |
11 | T 2400 3600 9 10 0 0 0 0 1 |
11 | T 3200 3600 9 10 0 0 0 0 1 |
12 | description=NXP 16/32-bit ARM926EJ-S microcontroller |
12 | description=NXP 16/32-bit ARM926EJ-S microcontroller |
13 | T 2400 3800 9 10 0 0 0 0 1 |
13 | T 3200 3800 9 10 0 0 0 0 1 |
14 | documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf |
14 | documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf |
15 | T 2600 2800 5 10 1 1 0 6 1 |
15 | T 3400 2800 5 10 1 1 0 6 1 |
16 | block=VDD (IO) |
16 | block=VDD (IO) |
17 | T 500 2800 5 10 1 1 0 0 1 |
17 | T 500 2800 5 10 1 1 0 0 1 |
18 | device=LPC3180FEL320 |
18 | device=LPC3180FEL320 |
19 | T 500 3000 5 10 1 1 0 0 1 |
19 | T 500 3000 5 10 1 1 0 0 1 |
20 | footprint=SOT824 |
20 | footprint=SOT824 |
21 | T 500 3200 5 10 1 1 0 0 1 |
21 | T 500 3200 5 10 1 1 0 0 1 |
22 | refdes=U? |
22 | refdes=U? |
23 | P 3100 600 2600 600 1 0 0 |
23 | P 3900 600 3400 600 1 0 0 |
24 | { |
24 | { |
25 | T 2550 600 9 10 1 1 0 7 1 |
25 | T 3350 600 9 10 1 1 0 7 1 |
26 | pinlabel=VDD_IOD |
26 | pinlabel=VDD_IOD |
27 | T 2700 650 5 8 1 1 0 0 1 |
27 | T 3500 650 5 8 1 1 0 0 1 |
28 | pinnumber=U4 |
28 | pinnumber=U4 |
29 | T 2700 650 5 8 0 1 0 0 1 |
29 | T 3500 650 5 8 0 1 0 0 1 |
30 | pinseq=U4 |
30 | pinseq=U4 |
31 | } |
31 | } |
32 | P 3100 1500 2600 1500 1 0 0 |
32 | P 3900 1500 3400 1500 1 0 0 |
33 | { |
33 | { |
34 | T 2550 1500 9 10 1 1 0 7 1 |
34 | T 3350 1500 9 10 1 1 0 7 1 |
35 | pinlabel=VDD_IOC |
35 | pinlabel=VDD_IOC |
36 | T 2700 1550 5 8 1 1 0 0 1 |
36 | T 3500 1550 5 8 1 1 0 0 1 |
37 | pinnumber=AC7 |
37 | pinnumber=AC7 |
38 | T 2700 1550 5 8 0 1 0 0 1 |
38 | T 3500 1550 5 8 0 1 0 0 1 |
39 | pinseq=AC7 |
39 | pinseq=AC7 |
40 | } |
40 | } |
41 | P 3100 2400 2600 2400 1 0 0 |
41 | P 3900 2400 3400 2400 1 0 0 |
42 | { |
42 | { |
43 | T 2550 2400 9 10 1 1 0 7 1 |
43 | T 3350 2400 9 10 1 1 0 7 1 |
44 | pinlabel=VDD_IOC |
44 | pinlabel=VDD_IOC |
45 | T 2700 2450 5 8 1 1 0 0 1 |
45 | T 3500 2450 5 8 1 1 0 0 1 |
46 | pinnumber=AA15 |
46 | pinnumber=AA15 |
47 | T 2700 2450 5 8 0 1 0 0 1 |
47 | T 3500 2450 5 8 0 1 0 0 1 |
48 | pinseq=AA15 |
48 | pinseq=AA15 |
49 | } |
49 | } |
50 | P 0 2100 500 2100 1 0 0 |
50 | P 0 2100 500 2100 1 0 0 |
51 | { |
51 | { |
52 | T 550 2100 9 10 1 1 0 1 1 |
52 | T 550 2100 9 10 1 1 0 1 1 |
Line 54... | Line 54... | ||
54 | T 400 2150 5 8 1 1 0 6 1 |
54 | T 400 2150 5 8 1 1 0 6 1 |
55 | pinnumber=B4 |
55 | pinnumber=B4 |
56 | T 400 2150 5 8 0 1 0 6 1 |
56 | T 400 2150 5 8 0 1 0 6 1 |
57 | pinseq=B4 |
57 | pinseq=B4 |
58 | } |
58 | } |
59 | P 3100 900 2600 900 1 0 0 |
59 | P 3900 900 3400 900 1 0 0 |
60 | { |
60 | { |
61 | T 2550 900 9 10 1 1 0 7 1 |
61 | T 3350 900 9 10 1 1 0 7 1 |
62 | pinlabel=VDD_IOD |
62 | pinlabel=VDD_IOD |
63 | T 2700 950 5 8 1 1 0 0 1 |
63 | T 3500 950 5 8 1 1 0 0 1 |
64 | pinnumber=G4 |
64 | pinnumber=G4 |
65 | T 2700 950 5 8 0 1 0 0 1 |
65 | T 3500 950 5 8 0 1 0 0 1 |
66 | pinseq=G4 |
66 | pinseq=G4 |
67 | } |
67 | } |
68 | P 0 2400 500 2400 1 0 0 |
68 | P 0 2400 500 2400 1 0 0 |
69 | { |
69 | { |
70 | T 550 2400 9 10 1 1 0 1 1 |
70 | T 550 2400 9 10 1 1 0 1 1 |
Line 72... | Line 72... | ||
72 | T 400 2450 5 8 1 1 0 6 1 |
72 | T 400 2450 5 8 1 1 0 6 1 |
73 | pinnumber=B7 |
73 | pinnumber=B7 |
74 | T 400 2450 5 8 0 1 0 6 1 |
74 | T 400 2450 5 8 0 1 0 6 1 |
75 | pinseq=B7 |
75 | pinseq=B7 |
76 | } |
76 | } |
77 | P 3100 2100 2600 2100 1 0 0 |
77 | P 3900 2100 3400 2100 1 0 0 |
78 | { |
78 | { |
79 | T 2550 2100 9 10 1 1 0 7 1 |
79 | T 3350 2100 9 10 1 1 0 7 1 |
80 | pinlabel=VDD_IOC |
80 | pinlabel=VDD_IOC |
81 | T 2700 2150 5 8 1 1 0 0 1 |
81 | T 3500 2150 5 8 1 1 0 0 1 |
82 | pinnumber=AA19 |
82 | pinnumber=AA19 |
83 | T 2700 2150 5 8 0 1 0 0 1 |
83 | T 3500 2150 5 8 0 1 0 0 1 |
84 | pinseq=AA19 |
84 | pinseq=AA19 |
85 | } |
85 | } |
86 | P 3100 1800 2600 1800 1 0 0 |
86 | P 3900 1800 3400 1800 1 0 0 |
87 | { |
87 | { |
88 | T 2550 1800 9 10 1 1 0 7 1 |
88 | T 3350 1800 9 10 1 1 0 7 1 |
89 | pinlabel=VDD_IOC |
89 | pinlabel=VDD_IOC |
90 | T 2700 1850 5 8 1 1 0 0 1 |
90 | T 3500 1850 5 8 1 1 0 0 1 |
91 | pinnumber=AB11 |
91 | pinnumber=AB11 |
92 | T 2700 1850 5 8 0 1 0 0 1 |
92 | T 3500 1850 5 8 0 1 0 0 1 |
93 | pinseq=AB11 |
93 | pinseq=AB11 |
94 | } |
94 | } |
95 | P 0 1500 500 1500 1 0 0 |
95 | P 0 1500 500 1500 1 0 0 |
96 | { |
96 | { |
97 | T 550 1500 9 10 1 1 0 1 1 |
97 | T 550 1500 9 10 1 1 0 1 1 |