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1 | v 20060123 1 |
1 | v 20060123 1 |
2 | B 300 300 1800 3000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
2 | B 500 300 1800 3000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
3 | T 2100 3400 9 10 0 0 0 0 1 |
3 | T 2100 3400 9 10 0 0 0 0 1 |
4 | uselicense=unlimited |
4 | uselicense=unlimited |
5 | T 2100 3600 9 10 0 0 0 0 1 |
5 | T 2100 3600 9 10 0 0 0 0 1 |
6 | distlicense=GPL (v2 or any later version) |
6 | distlicense=GPL (v2 or any later version) |
7 | T 2100 3800 9 10 0 0 0 0 1 |
7 | T 2100 3800 9 10 0 0 0 0 1 |
Line 10... | Line 10... | ||
10 | author=Tibor Palinkas |
10 | author=Tibor Palinkas |
11 | T 2100 4200 9 10 0 0 0 0 1 |
11 | T 2100 4200 9 10 0 0 0 0 1 |
12 | description=NXP 16/32-bit ARM926EJ-S microcontroller |
12 | description=NXP 16/32-bit ARM926EJ-S microcontroller |
13 | T 2100 4400 9 10 0 0 0 0 1 |
13 | T 2100 4400 9 10 0 0 0 0 1 |
14 | documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf |
14 | documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf |
15 | T 300 3400 5 10 1 1 0 0 1 |
15 | T 2300 3400 5 10 1 1 0 6 1 |
16 | block=VDD (RAM) |
16 | block=VDD (RAM) |
17 | T 300 3600 5 10 1 1 0 0 1 |
17 | T 500 3400 5 10 1 1 0 0 1 |
18 | device=LPC3180FEL320 |
18 | device=LPC3180FEL320 |
19 | T 300 3800 5 10 1 1 0 0 1 |
19 | T 500 3600 5 10 1 1 0 0 1 |
20 | footprint=SOT824 |
20 | footprint=SOT824 |
21 | T 300 4000 5 10 1 1 0 0 1 |
21 | T 500 3800 5 10 1 1 0 0 1 |
22 | refdes=U? |
22 | refdes=U? |
23 | P 0 2400 300 2400 1 0 0 |
23 | P 0 2400 500 2400 1 0 0 |
24 | { |
24 | { |
25 | T 350 2400 9 10 1 1 0 1 1 |
25 | T 550 2400 9 10 1 1 0 1 1 |
26 | pinlabel=VDD_RAM |
26 | pinlabel=VDD_RAM |
27 | T 200 2450 5 8 1 1 0 6 1 |
27 | T 400 2450 5 8 1 1 0 6 1 |
28 | pinnumber=F22 |
28 | pinnumber=F22 |
29 | T 200 2450 5 8 0 1 0 6 1 |
29 | T 400 2450 5 8 0 1 0 6 1 |
30 | pinseq=F22 |
30 | pinseq=F22 |
31 | } |
31 | } |
32 | P 0 600 300 600 1 0 0 |
32 | P 0 600 500 600 1 0 0 |
33 | { |
33 | { |
34 | T 350 600 9 10 1 1 0 1 1 |
34 | T 550 600 9 10 1 1 0 1 1 |
35 | pinlabel=VDD_RAM |
35 | pinlabel=VDD_RAM |
36 | T 200 650 5 8 1 1 0 6 1 |
36 | T 400 650 5 8 1 1 0 6 1 |
37 | pinnumber=Y21 |
37 | pinnumber=Y21 |
38 | T 200 650 5 8 0 1 0 6 1 |
38 | T 400 650 5 8 0 1 0 6 1 |
39 | pinseq=Y21 |
39 | pinseq=Y21 |
40 | } |
40 | } |
41 | P 0 3000 300 3000 1 0 0 |
41 | P 0 3000 500 3000 1 0 0 |
42 | { |
42 | { |
43 | T 350 3000 9 10 1 1 0 1 1 |
43 | T 550 3000 9 10 1 1 0 1 1 |
44 | pinlabel=VDD_RAM |
44 | pinlabel=VDD_RAM |
45 | T 200 3050 5 8 1 1 0 6 1 |
45 | T 400 3050 5 8 1 1 0 6 1 |
46 | pinnumber=AC24 |
46 | pinnumber=AC24 |
47 | T 200 3050 5 8 0 1 0 6 1 |
47 | T 400 3050 5 8 0 1 0 6 1 |
48 | pinseq=AC24 |
48 | pinseq=AC24 |
49 | } |
49 | } |
50 | P 0 1800 300 1800 1 0 0 |
50 | P 0 1800 500 1800 1 0 0 |
51 | { |
51 | { |
52 | T 350 1800 9 10 1 1 0 1 1 |
52 | T 550 1800 9 10 1 1 0 1 1 |
53 | pinlabel=VDD_RAM |
53 | pinlabel=VDD_RAM |
54 | T 200 1850 5 8 1 1 0 6 1 |
54 | T 400 1850 5 8 1 1 0 6 1 |
55 | pinnumber=J22 |
55 | pinnumber=J22 |
56 | T 200 1850 5 8 0 1 0 6 1 |
56 | T 400 1850 5 8 0 1 0 6 1 |
57 | pinseq=J22 |
57 | pinseq=J22 |
58 | } |
58 | } |
59 | P 0 900 300 900 1 0 0 |
59 | P 0 900 500 900 1 0 0 |
60 | { |
60 | { |
61 | T 350 900 9 10 1 1 0 1 1 |
61 | T 550 900 9 10 1 1 0 1 1 |
62 | pinlabel=VDD_RAM |
62 | pinlabel=VDD_RAM |
63 | T 200 950 5 8 1 1 0 6 1 |
63 | T 400 950 5 8 1 1 0 6 1 |
64 | pinnumber=U22 |
64 | pinnumber=U22 |
65 | T 200 950 5 8 0 1 0 6 1 |
65 | T 400 950 5 8 0 1 0 6 1 |
66 | pinseq=U22 |
66 | pinseq=U22 |
67 | } |
67 | } |
68 | P 0 2700 300 2700 1 0 0 |
68 | P 0 2700 500 2700 1 0 0 |
69 | { |
69 | { |
70 | T 350 2700 9 10 1 1 0 1 1 |
70 | T 550 2700 9 10 1 1 0 1 1 |
71 | pinlabel=VDD_RAM |
71 | pinlabel=VDD_RAM |
72 | T 200 2750 5 8 1 1 0 6 1 |
72 | T 400 2750 5 8 1 1 0 6 1 |
73 | pinnumber=AA20 |
73 | pinnumber=AA20 |
74 | T 200 2750 5 8 0 1 0 6 1 |
74 | T 400 2750 5 8 0 1 0 6 1 |
75 | pinseq=AA20 |
75 | pinseq=AA20 |
76 | } |
76 | } |
77 | P 0 1500 300 1500 1 0 0 |
77 | P 0 1500 500 1500 1 0 0 |
78 | { |
78 | { |
79 | T 350 1500 9 10 1 1 0 1 1 |
79 | T 550 1500 9 10 1 1 0 1 1 |
80 | pinlabel=VDD_RAM |
80 | pinlabel=VDD_RAM |
81 | T 200 1550 5 8 1 1 0 6 1 |
81 | T 400 1550 5 8 1 1 0 6 1 |
82 | pinnumber=K22 |
82 | pinnumber=K22 |
83 | T 200 1550 5 8 0 1 0 6 1 |
83 | T 400 1550 5 8 0 1 0 6 1 |
84 | pinseq=K22 |
84 | pinseq=K22 |
85 | } |
85 | } |
86 | P 0 1200 300 1200 1 0 0 |
86 | P 0 1200 500 1200 1 0 0 |
87 | { |
87 | { |
88 | T 350 1200 9 10 1 1 0 1 1 |
88 | T 550 1200 9 10 1 1 0 1 1 |
89 | pinlabel=VDD_RAM |
89 | pinlabel=VDD_RAM |
90 | T 200 1250 5 8 1 1 0 6 1 |
90 | T 400 1250 5 8 1 1 0 6 1 |
91 | pinnumber=P22 |
91 | pinnumber=P22 |
92 | T 200 1250 5 8 0 1 0 6 1 |
92 | T 400 1250 5 8 0 1 0 6 1 |
93 | pinseq=P22 |
93 | pinseq=P22 |
94 | } |
94 | } |
95 | P 0 2100 300 2100 1 0 0 |
95 | P 0 2100 500 2100 1 0 0 |
96 | { |
96 | { |
97 | T 350 2100 9 10 1 1 0 1 1 |
97 | T 550 2100 9 10 1 1 0 1 1 |
98 | pinlabel=VDD_RAM |
98 | pinlabel=VDD_RAM |
99 | T 200 2150 5 8 1 1 0 6 1 |
99 | T 400 2150 5 8 1 1 0 6 1 |
100 | pinnumber=G21 |
100 | pinnumber=G21 |
101 | T 200 2150 5 8 0 1 0 6 1 |
101 | T 400 2150 5 8 0 1 0 6 1 |
102 | pinseq=G21 |
102 | pinseq=G21 |
103 | } |
103 | } |