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v 20060123 1
B 300 300 3500 13200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 3800 13600 9 10 0 0 0 0 1
footprint=SOT824
T 3800 13800 9 10 0 0 0 0 1
description=arm9 microcontroller
T 3800 14000 9 10 0 0 0 0 1
device=LPC3180
T 3800 14200 9 10 0 0 0 0 1
distlicense=GPL (v2 or any later version)
T 3800 14400 9 10 0 0 0 0 1
uselicense=unlimited
T 3800 14600 9 10 0 0 0 0 1
author=Tibor Palinkas
T 3800 14800 9 10 0 0 0 0 1
copryright=2008 Tibor Palinkas
T 2100 12000 9 10 1 1 0 3 1
RAM
T 2100 12400 9 10 1 1 0 3 1
refdes=U?
T 2100 12800 9 10 1 1 0 3 1
LPC3180
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{
T 350 9500 9 10 1 1 0 1 1
pinlabel=RAM_A[09]
T 200 9550 5 8 1 1 0 6 1
pinnumber=AA23
T 200 9550 5 8 0 1 0 6 1
pinseq=AA23
}
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{
T 350 13100 9 10 1 1 0 1 1
pinlabel=RAM_A[00]
T 200 13150 5 8 1 1 0 6 1
pinnumber=AD22
T 200 13150 5 8 0 1 0 6 1
pinseq=AD22
}
P 4100 4700 3800 4700 1 0 0
{
T 3750 4700 9 10 1 1 0 7 1
pinlabel=RAM_D[21]
T 3900 4750 5 8 1 1 0 0 1
pinnumber=H24
T 3900 4750 5 8 0 1 0 0 1
pinseq=H24
}
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{
T 350 8300 9 10 1 1 0 1 1
pinlabel=RAM_A[12]
T 200 8350 5 8 1 1 0 6 1
pinnumber=Y23
T 200 8350 5 8 0 1 0 6 1
pinseq=Y23
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P 0 4700 300 4700 1 0 0
{
T 350 4700 9 10 1 1 0 1 1
pinlabel=RAM_CAS_N
T 200 4750 5 8 1 1 0 6 1
pinnumber=V23
T 200 4750 5 8 0 1 0 6 1
pinseq=V23
}
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{
T 3750 2700 9 10 1 1 0 7 1
pinlabel=RAM_D[26]
T 3900 2750 5 8 1 1 0 0 1
pinnumber=H23
T 3900 2750 5 8 0 1 0 0 1
pinseq=H23
}
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{
T 3750 7500 9 10 1 1 0 7 1
pinlabel=RAM_D[14]
T 3900 7550 5 8 1 1 0 0 1
pinnumber=M23
T 3900 7550 5 8 0 1 0 0 1
pinseq=M23
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P 0 3900 300 3900 1 0 0
{
T 350 3900 9 10 1 1 0 1 1
pinlabel=RAM_CLKIN
T 200 3950 5 8 1 1 0 6 1
pinnumber=T21
T 200 3950 5 8 0 1 0 6 1
pinseq=T21
}
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{
T 3750 11100 9 10 1 1 0 7 1
pinlabel=RAM_D[05]
T 3900 11150 5 8 1 1 0 0 1
pinnumber=R23
T 3900 11150 5 8 0 1 0 0 1
pinseq=R23
}
P 4100 13100 3800 13100 1 0 0
{
T 3750 13100 9 10 1 1 0 7 1
pinlabel=RAM_D[00]
T 3900 13150 5 8 1 1 0 0 1
pinnumber=T23
T 3900 13150 5 8 0 1 0 0 1
pinseq=T23
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P 0 9100 300 9100 1 0 0
{
T 350 9100 9 10 1 1 0 1 1
pinlabel=RAM_A[10]
T 200 9150 5 8 1 1 0 6 1
pinnumber=Y22
T 200 9150 5 8 0 1 0 6 1
pinseq=Y22
}
P 0 5900 300 5900 1 0 0
{
T 350 5900 9 10 1 1 0 1 1
pinlabel=RAM_DQM[2]
T 200 5950 5 8 1 1 0 6 1
pinnumber=V21
T 200 5950 5 8 0 1 0 6 1
pinseq=V21
}
P 4100 5500 3800 5500 1 0 0
{
T 3750 5500 9 10 1 1 0 7 1
pinlabel=RAM_D[19]
T 3900 5550 5 8 1 1 0 0 1
pinnumber=H21
T 3900 5550 5 8 0 1 0 0 1
pinseq=H21
}
P 4100 700 3800 700 1 0 0
{
T 3750 700 9 10 1 1 0 7 1
pinlabel=RAM_D[31]
T 3900 750 5 8 1 1 0 0 1
pinnumber=E24
T 3900 750 5 8 0 1 0 0 1
pinseq=E24
}
P 4100 11500 3800 11500 1 0 0
{
T 3750 11500 9 10 1 1 0 7 1
pinlabel=RAM_D[04]
T 3900 11550 5 8 1 1 0 0 1
pinnumber=P21
T 3900 11550 5 8 0 1 0 0 1
pinseq=P21
}
P 4100 3100 3800 3100 1 0 0
{
T 3750 3100 9 10 1 1 0 7 1
pinlabel=RAM_D[25]
T 3900 3150 5 8 1 1 0 0 1
pinnumber=J21
T 3900 3150 5 8 0 1 0 0 1
pinseq=J21
}
P 0 3500 300 3500 1 0 0
{
T 350 3500 9 10 1 1 0 1 1
pinlabel=RAM_RAS_N
T 200 3550 5 8 1 1 0 6 1
pinnumber=U21
T 200 3550 5 8 0 1 0 6 1
pinseq=U21
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P 0 7900 300 7900 1 0 0
{
T 350 7900 9 10 1 1 0 1 1
pinlabel=RAM_A[13]
T 200 7950 5 8 1 1 0 6 1
pinnumber=AA24
T 200 7950 5 8 0 1 0 6 1
pinseq=AA24
}
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{
T 3750 1500 9 10 1 1 0 7 1
pinlabel=RAM_D[29]
T 3900 1550 5 8 1 1 0 0 1
pinnumber=F21
T 3900 1550 5 8 0 1 0 0 1
pinseq=F21
}
P 0 2700 300 2700 1 0 0
{
T 350 2700 9 10 1 1 0 1 1
pinlabel=RAM_CKE
T 200 2750 5 8 1 1 0 6 1
pinnumber=U24
T 200 2750 5 8 0 1 0 6 1
pinseq=U24
}
P 0 3100 300 3100 1 0 0
{
T 350 3100 9 10 1 1 0 1 1
pinlabel=RAM_CLK
T 200 3150 5 8 1 1 0 6 1
pinnumber=U23
T 200 3150 5 8 0 1 0 6 1
pinseq=U23
}
P 0 11900 300 11900 1 0 0
{
T 350 11900 9 10 1 1 0 1 1
pinlabel=RAM_A[03]
T 200 11950 5 8 1 1 0 6 1
pinnumber=AD24
T 200 11950 5 8 0 1 0 6 1
pinseq=AD24
}
P 0 11500 300 11500 1 0 0
{
T 350 11500 9 10 1 1 0 1 1
pinlabel=RAM_A[04]
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pinnumber=AC22
T 200 11550 5 8 0 1 0 6 1
pinseq=AC22
}
P 4100 3500 3800 3500 1 0 0
{
T 3750 3500 9 10 1 1 0 7 1
pinlabel=RAM_D[24]
T 3900 3550 5 8 1 1 0 0 1
pinnumber=G23
T 3900 3550 5 8 0 1 0 0 1
pinseq=G23
}
P 4100 7100 3800 7100 1 0 0
{
T 3750 7100 9 10 1 1 0 7 1
pinlabel=RAM_D[15]
T 3900 7150 5 8 1 1 0 0 1
pinnumber=L24
T 3900 7150 5 8 0 1 0 0 1
pinseq=L24
}
P 0 5500 300 5500 1 0 0
{
T 350 5500 9 10 1 1 0 1 1
pinlabel=RAM_DQM[3]
T 200 5550 5 8 1 1 0 6 1
pinnumber=W24
T 200 5550 5 8 0 1 0 6 1
pinseq=W24
}
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{
T 3750 1100 9 10 1 1 0 7 1
pinlabel=RAM_D[30]
T 3900 1150 5 8 1 1 0 0 1
pinnumber=E23
T 3900 1150 5 8 0 1 0 0 1
pinseq=E23
}
P 4100 10300 3800 10300 1 0 0
{
T 3750 10300 9 10 1 1 0 7 1
pinlabel=RAM_D[08]
T 3900 10350 5 8 1 1 0 0 1
pinnumber=P23
T 3900 10350 5 8 0 1 0 0 1
pinseq=P23
}
P 0 10300 300 10300 1 0 0
{
T 350 10300 9 10 1 1 0 1 1
pinlabel=RAM_A[07]
T 200 10350 5 8 1 1 0 6 1
pinnumber=AB22
T 200 10350 5 8 0 1 0 6 1
pinseq=AB22
}
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{
T 3750 7900 9 10 1 1 0 7 1
pinlabel=RAM_D[13]
T 3900 7950 5 8 1 1 0 0 1
pinnumber=L22
T 3900 7950 5 8 0 1 0 0 1
pinseq=L22
}
P 4100 9900 3800 9900 1 0 0
{
T 3750 9900 9 10 1 1 0 7 1
pinlabel=RAM_D[07]
T 3900 9950 5 8 1 1 0 0 1
pinnumber=N21
T 3900 9950 5 8 0 1 0 0 1
pinseq=N21
}
P 4100 12300 3800 12300 1 0 0
{
T 3750 12300 9 10 1 1 0 7 1
pinlabel=RAM_D[02]
T 3900 12350 5 8 1 1 0 0 1
pinnumber=T24
T 3900 12350 5 8 0 1 0 0 1
pinseq=T24
}
P 0 6700 300 6700 1 0 0
{
T 350 6700 9 10 1 1 0 1 1
pinlabel=RAM_DQM[0]
T 200 6750 5 8 1 1 0 6 1
pinnumber=Y24
T 200 6750 5 8 0 1 0 6 1
pinseq=Y24
}
P 0 7500 300 7500 1 0 0
{
T 350 7500 9 10 1 1 0 1 1
pinlabel=RAM_A[14]
T 200 7550 5 8 1 1 0 6 1
pinnumber=W21
T 200 7550 5 8 0 1 0 6 1
pinseq=W21
}
P 4100 8300 3800 8300 1 0 0
{
T 3750 8300 9 10 1 1 0 7 1
pinlabel=RAM_D[12]
T 3900 8350 5 8 1 1 0 0 1
pinnumber=M24
T 3900 8350 5 8 0 1 0 0 1
pinseq=M24
}
P 4100 2300 3800 2300 1 0 0
{
T 3750 2300 9 10 1 1 0 7 1
pinlabel=RAM_D[27]
T 3900 2350 5 8 1 1 0 0 1
pinnumber=G24
T 3900 2350 5 8 0 1 0 0 1
pinseq=G24
}
P 0 11100 300 11100 1 0 0
{
T 350 11100 9 10 1 1 0 1 1
pinlabel=RAM_A[05]
T 200 11150 5 8 1 1 0 6 1
pinnumber=AA21
T 200 11150 5 8 0 1 0 6 1
pinseq=AA21
}
P 4100 6700 3800 6700 1 0 0
{
T 3750 6700 9 10 1 1 0 7 1
pinlabel=RAM_D[16]/DDR_DQS0
T 3900 6750 5 8 1 1 0 0 1
pinnumber=L23
T 3900 6750 5 8 0 1 0 0 1
pinseq=L23
}
P 4100 11900 3800 11900 1 0 0
{
T 3750 11900 9 10 1 1 0 7 1
pinlabel=RAM_D[03]
T 3900 11950 5 8 1 1 0 0 1
pinnumber=R24
T 3900 11950 5 8 0 1 0 0 1
pinseq=R24
}
P 0 12700 300 12700 1 0 0
{
T 350 12700 9 10 1 1 0 1 1
pinlabel=RAM_A[01]
T 200 12750 5 8 1 1 0 6 1
pinnumber=AB20
T 200 12750 5 8 0 1 0 6 1
pinseq=AB20
}
P 4100 1900 3800 1900 1 0 0
{
T 3750 1900 9 10 1 1 0 7 1
pinlabel=RAM_D[28]
T 3900 1950 5 8 1 1 0 0 1
pinnumber=F24
T 3900 1950 5 8 0 1 0 0 1
pinseq=F24
}
P 0 10700 300 10700 1 0 0
{
T 350 10700 9 10 1 1 0 1 1
pinlabel=RAM_A[06]
T 200 10750 5 8 1 1 0 6 1
pinnumber=AC23
T 200 10750 5 8 0 1 0 6 1
pinseq=AC23
}
P 4100 8700 3800 8700 1 0 0
{
T 3750 8700 9 10 1 1 0 7 1
pinlabel=RAM_D[11]
T 3900 8750 5 8 1 1 0 0 1
pinnumber=N23
T 3900 8750 5 8 0 1 0 0 1
pinseq=N23
}
P 4100 9500 3800 9500 1 0 0
{
T 3750 9500 9 10 1 1 0 7 1
pinlabel=RAM_D[09]
T 3900 9550 5 8 1 1 0 0 1
pinnumber=N24
T 3900 9550 5 8 0 1 0 0 1
pinseq=N24
}
P 0 12300 300 12300 1 0 0
{
T 350 12300 9 10 1 1 0 1 1
pinlabel=RAM_A[02]
T 200 12350 5 8 1 1 0 6 1
pinnumber=AD23
T 200 12350 5 8 0 1 0 6 1
pinseq=AD23
}
P 0 6300 300 6300 1 0 0
{
T 350 6300 9 10 1 1 0 1 1
pinlabel=RAM_DQM[1]
T 200 6350 5 8 1 1 0 6 1
pinnumber=W23
T 200 6350 5 8 0 1 0 6 1
pinseq=W23
}
P 4100 9100 3800 9100 1 0 0
{
T 3750 9100 9 10 1 1 0 7 1
pinlabel=RAM_D[10]
T 3900 9150 5 8 1 1 0 0 1
pinnumber=M22
T 3900 9150 5 8 0 1 0 0 1
pinseq=M22
}
P 4100 5900 3800 5900 1 0 0
{
T 3750 5900 9 10 1 1 0 7 1
pinlabel=RAM_D[18]/DDR_NCLK
T 3900 5950 5 8 1 1 0 0 1
pinnumber=K24
T 3900 5950 5 8 0 1 0 0 1
pinseq=K24
}
P 4100 5100 3800 5100 1 0 0
{
T 3750 5100 9 10 1 1 0 7 1
pinlabel=RAM_D[20]
T 3900 5150 5 8 1 1 0 0 1
pinnumber=J24
T 3900 5150 5 8 0 1 0 0 1
pinseq=J24
}
P 0 9900 300 9900 1 0 0
{
T 350 9900 9 10 1 1 0 1 1
pinlabel=RAM_A[08]
T 200 9950 5 8 1 1 0 6 1
pinnumber=AB23
T 200 9950 5 8 0 1 0 6 1
pinseq=AB23
}
P 0 8700 300 8700 1 0 0
{
T 350 8700 9 10 1 1 0 1 1
pinlabel=RAM_A[11]
T 200 8750 5 8 1 1 0 6 1
pinnumber=AB24
T 200 8750 5 8 0 1 0 6 1
pinseq=AB24
}
P 4100 3900 3800 3900 1 0 0
{
T 3750 3900 9 10 1 1 0 7 1
pinlabel=RAM_D[23]
T 3900 3950 5 8 1 1 0 0 1
pinnumber=H22
T 3900 3950 5 8 0 1 0 0 1
pinseq=H22
}
P 0 4300 300 4300 1 0 0
{
T 350 4300 9 10 1 1 0 1 1
pinlabel=RAM_CS_N
T 200 4350 5 8 1 1 0 6 1
pinnumber=V24
T 200 4350 5 8 0 1 0 6 1
pinseq=V24
}
P 4100 6300 3800 6300 1 0 0
{
T 3750 6300 9 10 1 1 0 7 1
pinlabel=RAM_D[17]/DDR_DQS1
T 3900 6350 5 8 1 1 0 0 1
pinnumber=L21
T 3900 6350 5 8 0 1 0 0 1
pinseq=L21
}
P 4100 10700 3800 10700 1 0 0
{
T 3750 10700 9 10 1 1 0 7 1
pinlabel=RAM_D[06]
T 3900 10750 5 8 1 1 0 0 1
pinnumber=P24
T 3900 10750 5 8 0 1 0 0 1
pinseq=P24
}
P 4100 12700 3800 12700 1 0 0
{
T 3750 12700 9 10 1 1 0 7 1
pinlabel=RAM_D[01]
T 3900 12750 5 8 1 1 0 0 1
pinnumber=T22
T 3900 12750 5 8 0 1 0 0 1
pinseq=T22
}
P 4100 4300 3800 4300 1 0 0
{
T 3750 4300 9 10 1 1 0 7 1
pinlabel=RAM_D[22]
T 3900 4350 5 8 1 1 0 0 1
pinnumber=K23
T 3900 4350 5 8 0 1 0 0 1
pinseq=K23
}
P 0 5100 300 5100 1 0 0
{
T 350 5100 9 10 1 1 0 1 1
pinlabel=RAM_WR_N
T 200 5150 5 8 1 1 0 6 1
pinnumber=V22
T 200 5150 5 8 0 1 0 6 1
pinseq=V22
}