Subversion Repositories OpenARM Single-board Computer

v 20080127 1
C 40000 40000 0 0 0 title-bordered-A1.sym
C 51300 44700 1 0 0 MT48LC16M16A2.sym
{
T 54800 55700 5 10 0 0 0 0 1
footprint=TSOPII54
T 51600 54700 5 10 1 1 0 0 1
device=MT48LC16M16A2P-7E
T 51600 54900 5 10 1 1 0 0 1
refdes=U?
}
C 42700 44700 1 0 0 LPC3180-RAM.sym
{
T 46800 58300 5 10 0 0 0 0 1
footprint=SOT824
T 46800 58700 5 10 0 0 0 0 1
device=LPC3180
T 43200 55100 5 10 1 1 0 0 1
refdes=U?
}
N 55100 46800 55400 46800 4
N 55400 46500 55100 46500 4
N 55100 46200 55400 46200 4
N 55100 45900 55400 45900 4
N 55100 45600 55400 45600 4
N 55100 45300 55400 45300 4
N 55100 45000 55400 45000 4
C 55300 44500 1 0 0 gnd-1.sym
N 55400 44800 55400 46800 4
C 56300 46200 1 90 0 capacitor-1.sym
{
T 55600 46400 5 10 0 0 90 0 1
device=CAPACITOR
T 55800 46400 5 10 1 1 90 0 1
refdes=C?
T 55400 46400 5 10 0 0 90 0 1
symversion=0.1
T 56300 46200 5 10 0 0 90 0 1
footprint=0805
T 56400 46400 5 10 1 1 90 2 1
value=100nF
}
C 57300 46200 1 90 0 capacitor-1.sym
{
T 56600 46400 5 10 0 0 90 0 1
device=CAPACITOR
T 56800 46400 5 10 1 1 90 0 1
refdes=C?
T 56400 46400 5 10 0 0 90 0 1
symversion=0.1
T 57300 46200 5 10 0 0 90 0 1
footprint=0805
T 57400 46400 5 10 1 1 90 2 1
value=100nF
}
C 58300 46200 1 90 0 capacitor-1.sym
{
T 57600 46400 5 10 0 0 90 0 1
device=CAPACITOR
T 57800 46400 5 10 1 1 90 0 1
refdes=C?
T 57400 46400 5 10 0 0 90 0 1
symversion=0.1
T 58300 46200 5 10 0 0 90 0 1
footprint=0805
T 58400 46400 5 10 1 1 90 2 1
value=100nF
}
C 59300 46200 1 90 0 capacitor-1.sym
{
T 58600 46400 5 10 0 0 90 0 1
device=CAPACITOR
T 58800 46400 5 10 1 1 90 0 1
refdes=C?
T 58400 46400 5 10 0 0 90 0 1
symversion=0.1
T 59300 46200 5 10 0 0 90 0 1
footprint=0805
T 59400 46400 5 10 1 1 90 2 1
value=100nF
}
N 55100 49200 56100 49200 4
N 55100 48900 57100 48900 4
N 57100 48900 57100 47100 4
N 55100 48600 58100 48600 4
N 58100 48600 58100 47100 4
N 55100 48300 59100 48300 4
N 59100 48300 59100 47100 4
C 60300 46200 1 90 0 capacitor-1.sym
{
T 59600 46400 5 10 0 0 90 0 1
device=CAPACITOR
T 59800 46400 5 10 1 1 90 0 1
refdes=C?
T 59400 46400 5 10 0 0 90 0 1
symversion=0.1
T 60300 46200 5 10 0 0 90 0 1
footprint=0805
T 60400 46400 5 10 1 1 90 2 1
value=100nF
}
N 55100 48000 60100 48000 4
N 60100 48000 60100 47100 4
C 61300 46200 1 90 0 capacitor-1.sym
{
T 60600 46400 5 10 0 0 90 0 1
device=CAPACITOR
T 60800 46400 5 10 1 1 90 0 1
refdes=C?
T 60400 46400 5 10 0 0 90 0 1
symversion=0.1
T 61300 46200 5 10 0 0 90 0 1
footprint=0805
T 61400 46400 5 10 1 1 90 2 1
value=100nF
}
C 62300 46200 1 90 0 capacitor-1.sym
{
T 61600 46400 5 10 0 0 90 0 1
device=CAPACITOR
T 61800 46400 5 10 1 1 90 0 1
refdes=C?
T 61400 46400 5 10 0 0 90 0 1
symversion=0.1
T 62300 46200 5 10 0 0 90 0 1
footprint=0805
T 62400 46400 5 10 1 1 90 2 1
value=100nF
}
N 55100 47700 61100 47700 4
N 61100 47700 61100 47100 4
N 55100 47400 62100 47400 4
N 62100 47400 62100 47100 4
C 56000 45700 1 0 0 gnd-1.sym
N 56100 46200 56100 46000 4
N 57100 46200 57100 46000 4
C 57000 45700 1 0 0 gnd-1.sym
N 58100 46200 58100 46000 4
C 58000 45700 1 0 0 gnd-1.sym
N 59100 46200 59100 46000 4
C 59000 45700 1 0 0 gnd-1.sym
N 60100 46200 60100 46000 4
C 60000 45700 1 0 0 gnd-1.sym
N 61100 46200 61100 46000 4
C 61000 45700 1 0 0 gnd-1.sym
N 62100 46200 62100 46000 4
C 62000 45700 1 0 0 gnd-1.sym
C 55900 49200 1 0 0 generic-power.sym
{
T 56100 49450 5 10 1 1 0 3 1
net=+3.125V:1
}
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N 56100 48600 56100 48300 4
N 56100 48300 56100 48000 4
N 56100 48000 56100 47700 4
N 56100 47700 56100 47400 4
N 56100 47400 56100 47100 4
N 55100 54300 56425 54300 4
{
T 55200 54350 5 10 1 1 0 0 1
netname=RAM_D[00]
}
N 55100 54000 56425 54000 4
{
T 55200 54050 5 10 1 1 0 0 1
netname=RAM_D[01]
}
N 55100 53700 56425 53700 4
{
T 55200 53750 5 10 1 1 0 0 1
netname=RAM_D[02]
}
N 55100 53400 56425 53400 4
{
T 55200 53450 5 10 1 1 0 0 1
netname=RAM_D[03]
}
N 55100 53100 56425 53100 4
{
T 55200 53150 5 10 1 1 0 0 1
netname=RAM_D[04]
}
N 55100 52800 56425 52800 4
{
T 55200 52850 5 10 1 1 0 0 1
netname=RAM_D[05]
}
N 55100 52500 56425 52500 4
{
T 55200 52550 5 10 1 1 0 0 1
netname=RAM_D[06]
}
N 55100 52200 56425 52200 4
{
T 55200 52250 5 10 1 1 0 0 1
netname=RAM_D[07]
}
N 55100 51900 56425 51900 4
{
T 55200 51950 5 10 1 1 0 0 1
netname=RAM_D[08]
}
N 55100 51600 56425 51600 4
{
T 55200 51650 5 10 1 1 0 0 1
netname=RAM_D[09]
}
N 55100 51300 56425 51300 4
{
T 55200 51350 5 10 1 1 0 0 1
netname=RAM_D[10]
}
N 55100 51000 56425 51000 4
{
T 55200 51050 5 10 1 1 0 0 1
netname=RAM_D[11]
}
N 55100 50700 56425 50700 4
{
T 55200 50750 5 10 1 1 0 0 1
netname=RAM_D[12]
}
N 55100 50400 56425 50400 4
{
T 55200 50450 5 10 1 1 0 0 1
netname=RAM_D[13]
}
N 55100 50100 56425 50100 4
{
T 55200 50150 5 10 1 1 0 0 1
netname=RAM_D[14]
}
N 55100 49800 56425 49800 4
{
T 55200 49850 5 10 1 1 0 0 1
netname=RAM_D[15]
}
N 51300 54300 49900 54300 4
{
T 51200 54350 5 10 1 1 0 6 1
netname=RAM_A[00]
}
N 51300 54000 49900 54000 4
{
T 51200 54050 5 10 1 1 0 6 1
netname=RAM_A[01]
}
N 51300 53700 49900 53700 4
{
T 51200 53750 5 10 1 1 0 6 1
netname=RAM_A[02]
}
N 51300 53400 49900 53400 4
{
T 51200 53450 5 10 1 1 0 6 1
netname=RAM_A[03]
}
N 51300 53100 49900 53100 4
{
T 51200 53150 5 10 1 1 0 6 1
netname=RAM_A[04]
}
N 51300 52800 49900 52800 4
{
T 51200 52850 5 10 1 1 0 6 1
netname=RAM_A[05]
}
N 51300 52500 49900 52500 4
{
T 51200 52550 5 10 1 1 0 6 1
netname=RAM_A[06]
}
N 51300 52200 49900 52200 4
{
T 51200 52250 5 10 1 1 0 6 1
netname=RAM_A[07]
}
N 51300 51900 49900 51900 4
{
T 51200 51950 5 10 1 1 0 6 1
netname=RAM_A[08]
}
N 51300 51600 49900 51600 4
{
T 51200 51650 5 10 1 1 0 6 1
netname=RAM_A[09]
}
N 51300 51300 49900 51300 4
{
T 51200 51350 5 10 1 1 0 6 1
netname=RAM_A[10]
}
N 51300 51000 49900 51000 4
{
T 51200 51050 5 10 1 1 0 6 1
netname=RAM_A[11]
}
N 51300 50700 49900 50700 4
{
T 51200 50750 5 10 1 1 0 6 1
netname=RAM_A[12]
}
N 51300 50100 49900 50100 4
{
T 51200 50150 5 10 1 1 0 6 1
netname=RAM_A[13]
}
N 51300 49800 49900 49800 4
{
T 51200 49850 5 10 1 1 0 6 1
netname=RAM_A[14]
}
N 49700 47100 51300 47100 4
{
T 51200 47150 5 10 1 1 0 6 1
netname=RAM_DQM[0]
}
N 49700 46800 51300 46800 4
{
T 51200 46850 5 10 1 1 0 6 1
netname=RAM_DQM[1]
}
N 49700 47700 51300 47700 4
{
T 51200 47750 5 10 1 1 0 6 1
netname=RAM_CKE
}
N 49700 48000 51300 48000 4
{
T 51200 48050 5 10 1 1 0 6 1
netname=RAM_CLK
}
N 49700 46200 51300 46200 4
{
T 51200 46250 5 10 1 1 0 6 1
netname=RAM_CAS_N
}
N 49700 45900 51300 45900 4
{
T 51200 45950 5 10 1 1 0 6 1
netname=RAM_RAS_N
}
N 49700 45300 51300 45300 4
{
T 51200 45350 5 10 1 1 0 6 1
netname=RAM_WR_N
}
N 49700 45000 51300 45000 4
{
T 51200 45050 5 10 1 1 0 6 1
netname=RAM_CS_N
}
N 41200 54300 42900 54300 4
{
T 42500 54350 5 10 1 1 0 6 1
netname=RAM_A[00]
}
N 41200 54000 42900 54000 4
{
T 42500 54050 5 10 1 1 0 6 1
netname=RAM_A[01]
}
N 41200 53700 42900 53700 4
{
T 42500 53750 5 10 1 1 0 6 1
netname=RAM_A[02]
}
N 41200 53400 42900 53400 4
{
T 42500 53450 5 10 1 1 0 6 1
netname=RAM_A[03]
}
N 41200 53100 42900 53100 4
{
T 42500 53150 5 10 1 1 0 6 1
netname=RAM_A[04]
}
N 41200 52800 42900 52800 4
{
T 42500 52850 5 10 1 1 0 6 1
netname=RAM_A[05]
}
N 41200 52500 42900 52500 4
{
T 42500 52550 5 10 1 1 0 6 1
netname=RAM_A[06]
}
N 41200 52200 42900 52200 4
{
T 42500 52250 5 10 1 1 0 6 1
netname=RAM_A[07]
}
N 41200 51900 42900 51900 4
{
T 42500 51950 5 10 1 1 0 6 1
netname=RAM_A[08]
}
N 41200 51600 42900 51600 4
{
T 42500 51650 5 10 1 1 0 6 1
netname=RAM_A[09]
}
N 41200 51300 42900 51300 4
{
T 42500 51350 5 10 1 1 0 6 1
netname=RAM_A[10]
}
N 41200 51000 42900 51000 4
{
T 42500 51050 5 10 1 1 0 6 1
netname=RAM_A[11]
}
N 41200 50700 42900 50700 4
{
T 42500 50750 5 10 1 1 0 6 1
netname=RAM_A[12]
}
N 41200 50400 42900 50400 4
{
T 42500 50450 5 10 1 1 0 6 1
netname=RAM_A[13]
}
N 41200 50100 42900 50100 4
{
T 42500 50150 5 10 1 1 0 6 1
netname=RAM_A[14]
}
N 41200 49500 42900 49500 4
{
T 42500 49550 5 10 1 1 0 6 1
netname=RAM_DQM[0]
}
N 41200 49200 42900 49200 4
{
T 42500 49250 5 10 1 1 0 6 1
netname=RAM_DQM[1]
}
N 41200 48000 42900 48000 4
{
T 42500 48050 5 10 1 1 0 6 1
netname=RAM_CAS_N
}
N 41200 47700 42900 47700 4
{
T 42500 47750 5 10 1 1 0 6 1
netname=RAM_RAS_N
}
N 41200 45900 42900 45900 4
{
T 42500 45950 5 10 1 1 0 6 1
netname=RAM_WR_N
}
N 41200 45600 42900 45600 4
{
T 42500 45650 5 10 1 1 0 6 1
netname=RAM_CS_N
}
N 41200 46500 42900 46500 4
{
T 42500 46550 5 10 1 1 0 6 1
netname=RAM_CKE
}
N 41200 46800 42900 46800 4
{
T 42500 46850 5 10 1 1 0 6 1
netname=RAM_CLK
}
N 47300 54300 48625 54300 4
{
T 47600 54350 5 10 1 1 0 0 1
netname=RAM_D[00]
}
N 47300 54000 48625 54000 4
{
T 47600 54050 5 10 1 1 0 0 1
netname=RAM_D[01]
}
N 47300 53700 48625 53700 4
{
T 47600 53750 5 10 1 1 0 0 1
netname=RAM_D[02]
}
N 47300 53400 48625 53400 4
{
T 47600 53450 5 10 1 1 0 0 1
netname=RAM_D[03]
}
N 47300 53100 48625 53100 4
{
T 47600 53150 5 10 1 1 0 0 1
netname=RAM_D[04]
}
N 47300 52800 48625 52800 4
{
T 47600 52850 5 10 1 1 0 0 1
netname=RAM_D[05]
}
N 47300 52500 48625 52500 4
{
T 47600 52550 5 10 1 1 0 0 1
netname=RAM_D[06]
}
N 47300 52200 48625 52200 4
{
T 47600 52250 5 10 1 1 0 0 1
netname=RAM_D[07]
}
N 47300 51900 48625 51900 4
{
T 47600 51950 5 10 1 1 0 0 1
netname=RAM_D[08]
}
N 47300 51600 48625 51600 4
{
T 47600 51650 5 10 1 1 0 0 1
netname=RAM_D[09]
}
N 47300 51300 48625 51300 4
{
T 47600 51350 5 10 1 1 0 0 1
netname=RAM_D[10]
}
N 47300 51000 48625 51000 4
{
T 47600 51050 5 10 1 1 0 0 1
netname=RAM_D[11]
}
N 47300 50700 48625 50700 4
{
T 47600 50750 5 10 1 1 0 0 1
netname=RAM_D[12]
}
N 47300 50400 48625 50400 4
{
T 47600 50450 5 10 1 1 0 0 1
netname=RAM_D[13]
}
N 47300 50100 48625 50100 4
{
T 47600 50150 5 10 1 1 0 0 1
netname=RAM_D[14]
}
N 47300 49800 48625 49800 4
{
T 47600 49850 5 10 1 1 0 0 1
netname=RAM_D[15]
}