Subversion Repositories OpenARM Single-board Computer

v 20080127 1
C 40000 40000 0 0 0 title-bordered-A1.sym
N 61100 54100 61400 54100 4
N 61400 53800 61100 53800 4
N 61100 53500 61400 53500 4
N 61100 53200 61400 53200 4
N 61100 52900 61400 52900 4
N 61100 52600 61400 52600 4
N 61100 52300 61400 52300 4
C 61300 51800 1 0 0 gnd-1.sym
N 61400 52100 61400 54100 4
C 62300 53500 1 90 0 capacitor-1.sym
{
T 61600 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 61800 53700 5 10 1 1 90 0 1
refdes=C408
T 61400 53700 5 10 0 0 90 0 1
symversion=0.1
T 62300 53500 5 10 0 0 90 0 1
footprint=0805
T 62400 53700 5 10 1 1 90 2 1
value=100nF
}
C 63300 53500 1 90 0 capacitor-1.sym
{
T 62600 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 62800 53700 5 10 1 1 90 0 1
refdes=C409
T 62400 53700 5 10 0 0 90 0 1
symversion=0.1
T 63300 53500 5 10 0 0 90 0 1
footprint=0805
T 63400 53700 5 10 1 1 90 2 1
value=100nF
}
C 64300 53500 1 90 0 capacitor-1.sym
{
T 63600 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 63800 53700 5 10 1 1 90 0 1
refdes=C410
T 63400 53700 5 10 0 0 90 0 1
symversion=0.1
T 64300 53500 5 10 0 0 90 0 1
footprint=0805
T 64400 53700 5 10 1 1 90 2 1
value=100nF
}
C 65300 53500 1 90 0 capacitor-1.sym
{
T 64600 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 64800 53700 5 10 1 1 90 0 1
refdes=C411
T 64400 53700 5 10 0 0 90 0 1
symversion=0.1
T 65300 53500 5 10 0 0 90 0 1
footprint=0805
T 65400 53700 5 10 1 1 90 2 1
value=100nF
}
N 61100 56500 62100 56500 4
N 61100 56200 63100 56200 4
N 63100 56200 63100 54400 4
N 61100 55900 64100 55900 4
N 64100 55900 64100 54400 4
N 61100 55600 65100 55600 4
N 65100 55600 65100 54400 4
C 66300 53500 1 90 0 capacitor-1.sym
{
T 65600 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 65800 53700 5 10 1 1 90 0 1
refdes=C412
T 65400 53700 5 10 0 0 90 0 1
symversion=0.1
T 66300 53500 5 10 0 0 90 0 1
footprint=0805
T 66400 53700 5 10 1 1 90 2 1
value=100nF
}
N 61100 55300 66100 55300 4
N 66100 55300 66100 54400 4
C 67300 53500 1 90 0 capacitor-1.sym
{
T 66600 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 66800 53700 5 10 1 1 90 0 1
refdes=C413
T 66400 53700 5 10 0 0 90 0 1
symversion=0.1
T 67300 53500 5 10 0 0 90 0 1
footprint=0805
T 67400 53700 5 10 1 1 90 2 1
value=100nF
}
C 68300 53500 1 90 0 capacitor-1.sym
{
T 67600 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 67800 53700 5 10 1 1 90 0 1
refdes=C414
T 67400 53700 5 10 0 0 90 0 1
symversion=0.1
T 68300 53500 5 10 0 0 90 0 1
footprint=0805
T 68400 53700 5 10 1 1 90 2 1
value=100nF
}
N 61100 55000 67100 55000 4
N 67100 55000 67100 54400 4
N 61100 54700 68100 54700 4
N 68100 54700 68100 54400 4
C 62000 53000 1 0 0 gnd-1.sym
N 62100 53500 62100 53300 4
N 63100 53500 63100 53300 4
C 63000 53000 1 0 0 gnd-1.sym
N 64100 53500 64100 53300 4
C 64000 53000 1 0 0 gnd-1.sym
N 65100 53500 65100 53300 4
C 65000 53000 1 0 0 gnd-1.sym
N 66100 53500 66100 53300 4
C 66000 53000 1 0 0 gnd-1.sym
N 67100 53500 67100 53300 4
C 67000 53000 1 0 0 gnd-1.sym
N 68100 53500 68100 53300 4
C 68000 53000 1 0 0 gnd-1.sym
C 61900 56500 1 0 0 generic-power.sym
{
T 62100 56750 5 10 1 1 0 3 1
net=+3.125V:1
}
N 62100 56200 62100 56500 4
N 62100 56200 62100 55900 4
N 62100 55900 62100 55600 4
N 62100 55600 62100 55300 4
N 62100 55300 62100 55000 4
N 62100 55000 62100 54700 4
N 62100 54700 62100 54400 4
N 61100 61600 62425 61600 4
{
T 61200 61650 5 10 1 1 0 0 1
netname=RAM_D[16]
}
N 61100 61300 62425 61300 4
{
T 61200 61350 5 10 1 1 0 0 1
netname=RAM_D[17]
}
N 61100 61000 62425 61000 4
{
T 61200 61050 5 10 1 1 0 0 1
netname=RAM_D[18]
}
N 61100 60700 62425 60700 4
{
T 61200 60750 5 10 1 1 0 0 1
netname=RAM_D[19]
}
N 61100 60400 62425 60400 4
{
T 61200 60450 5 10 1 1 0 0 1
netname=RAM_D[20]
}
N 61100 60100 62425 60100 4
{
T 61200 60150 5 10 1 1 0 0 1
netname=RAM_D[21]
}
N 61100 59800 62425 59800 4
{
T 61200 59850 5 10 1 1 0 0 1
netname=RAM_D[22]
}
N 61100 59500 62425 59500 4
{
T 61200 59550 5 10 1 1 0 0 1
netname=RAM_D[23]
}
N 61100 59200 62425 59200 4
{
T 61200 59250 5 10 1 1 0 0 1
netname=RAM_D[24]
}
N 61100 58900 62425 58900 4
{
T 61200 58950 5 10 1 1 0 0 1
netname=RAM_D[25]
}
N 61100 58600 62425 58600 4
{
T 61200 58650 5 10 1 1 0 0 1
netname=RAM_D[26]
}
N 61100 58300 62425 58300 4
{
T 61200 58350 5 10 1 1 0 0 1
netname=RAM_D[27]
}
N 61100 58000 62425 58000 4
{
T 61200 58050 5 10 1 1 0 0 1
netname=RAM_D[28]
}
N 61100 57700 62425 57700 4
{
T 61200 57750 5 10 1 1 0 0 1
netname=RAM_D[29]
}
N 61100 57400 62425 57400 4
{
T 61200 57450 5 10 1 1 0 0 1
netname=RAM_D[30]
}
N 61100 57100 62425 57100 4
{
T 61200 57150 5 10 1 1 0 0 1
netname=RAM_D[31]
}
N 57300 61600 55900 61600 4
{
T 57200 61650 5 10 1 1 0 6 1
netname=RAM_A[00]
}
N 57300 61300 55900 61300 4
{
T 57200 61350 5 10 1 1 0 6 1
netname=RAM_A[01]
}
N 57300 61000 55900 61000 4
{
T 57200 61050 5 10 1 1 0 6 1
netname=RAM_A[02]
}
N 57300 60700 55900 60700 4
{
T 57200 60750 5 10 1 1 0 6 1
netname=RAM_A[03]
}
N 57300 60400 55900 60400 4
{
T 57200 60450 5 10 1 1 0 6 1
netname=RAM_A[04]
}
N 57300 60100 55900 60100 4
{
T 57200 60150 5 10 1 1 0 6 1
netname=RAM_A[05]
}
N 57300 59800 55900 59800 4
{
T 57200 59850 5 10 1 1 0 6 1
netname=RAM_A[06]
}
N 57300 59500 55900 59500 4
{
T 57200 59550 5 10 1 1 0 6 1
netname=RAM_A[07]
}
N 57300 59200 55900 59200 4
{
T 57200 59250 5 10 1 1 0 6 1
netname=RAM_A[08]
}
N 57300 58900 55900 58900 4
{
T 57200 58950 5 10 1 1 0 6 1
netname=RAM_A[09]
}
N 57300 58600 55900 58600 4
{
T 57200 58650 5 10 1 1 0 6 1
netname=RAM_A[10]
}
N 57300 58300 55900 58300 4
{
T 57200 58350 5 10 1 1 0 6 1
netname=RAM_A[11]
}
N 57300 58000 55900 58000 4
{
T 57200 58050 5 10 1 1 0 6 1
netname=RAM_A[12]
}
N 57300 57400 55900 57400 4
{
T 57200 57450 5 10 1 1 0 6 1
netname=RAM_A[13]
}
N 57300 57100 55900 57100 4
{
T 57200 57150 5 10 1 1 0 6 1
netname=RAM_A[14]
}
N 55700 54400 57300 54400 4
{
T 57200 54450 5 10 1 1 0 6 1
netname=RAM_DQM[2]
}
N 55700 54100 57300 54100 4
{
T 57200 54150 5 10 1 1 0 6 1
netname=RAM_DQM[3]
}
N 55700 55000 57300 55000 4
{
T 57200 55050 5 10 1 1 0 6 1
netname=RAM_CKE
}
N 55700 55300 57300 55300 4
{
T 57200 55350 5 10 1 1 0 6 1
netname=RAM_CLK
}
N 55700 53500 57300 53500 4
{
T 57200 53550 5 10 1 1 0 6 1
netname=RAM_CAS_N
}
N 55700 53200 57300 53200 4
{
T 57200 53250 5 10 1 1 0 6 1
netname=RAM_RAS_N
}
N 55700 52600 57300 52600 4
{
T 57200 52650 5 10 1 1 0 6 1
netname=RAM_WR_N
}
N 55700 52300 57300 52300 4
{
T 57200 52350 5 10 1 1 0 6 1
netname=RAM_CS_N
}
N 41700 50600 43400 50600 4
{
T 43000 50650 5 10 1 1 0 6 1
netname=RAM_A[00]
}
N 41700 50300 43400 50300 4
{
T 43000 50350 5 10 1 1 0 6 1
netname=RAM_A[01]
}
N 41700 50000 43400 50000 4
{
T 43000 50050 5 10 1 1 0 6 1
netname=RAM_A[02]
}
N 41700 49700 43400 49700 4
{
T 43000 49750 5 10 1 1 0 6 1
netname=RAM_A[03]
}
N 41700 49400 43400 49400 4
{
T 43000 49450 5 10 1 1 0 6 1
netname=RAM_A[04]
}
N 41700 49100 43400 49100 4
{
T 43000 49150 5 10 1 1 0 6 1
netname=RAM_A[05]
}
N 41700 48800 43400 48800 4
{
T 43000 48850 5 10 1 1 0 6 1
netname=RAM_A[06]
}
N 41700 48500 43400 48500 4
{
T 43000 48550 5 10 1 1 0 6 1
netname=RAM_A[07]
}
N 41700 48200 43400 48200 4
{
T 43000 48250 5 10 1 1 0 6 1
netname=RAM_A[08]
}
N 41700 47900 43400 47900 4
{
T 43000 47950 5 10 1 1 0 6 1
netname=RAM_A[09]
}
N 41700 47600 43400 47600 4
{
T 43000 47650 5 10 1 1 0 6 1
netname=RAM_A[10]
}
N 41700 47300 43400 47300 4
{
T 43000 47350 5 10 1 1 0 6 1
netname=RAM_A[11]
}
N 41700 47000 43400 47000 4
{
T 43000 47050 5 10 1 1 0 6 1
netname=RAM_A[12]
}
N 41700 46700 43400 46700 4
{
T 43000 46750 5 10 1 1 0 6 1
netname=RAM_A[13]
}
N 41700 46400 43400 46400 4
{
T 43000 46450 5 10 1 1 0 6 1
netname=RAM_A[14]
}
N 41700 45800 43400 45800 4
{
T 43000 45850 5 10 1 1 0 6 1
netname=RAM_DQM[0]
}
N 41700 45500 43400 45500 4
{
T 43000 45550 5 10 1 1 0 6 1
netname=RAM_DQM[1]
}
N 41700 44300 43400 44300 4
{
T 43000 44350 5 10 1 1 0 6 1
netname=RAM_CAS_N
}
N 41700 44000 43400 44000 4
{
T 43000 44050 5 10 1 1 0 6 1
netname=RAM_RAS_N
}
N 41700 42200 43400 42200 4
{
T 43000 42250 5 10 1 1 0 6 1
netname=RAM_WR_N
}
N 41700 41900 43400 41900 4
{
T 43000 41950 5 10 1 1 0 6 1
netname=RAM_CS_N
}
N 41700 42800 43400 42800 4
{
T 43000 42850 5 10 1 1 0 6 1
netname=RAM_CKE
}
N 41700 43100 43400 43100 4
{
T 43000 43150 5 10 1 1 0 6 1
netname=RAM_CLK
}
N 47800 50600 49200 50600 4
{
T 48100 50650 5 10 1 1 0 0 1
netname=RAM_D[00]
}
N 47800 50300 49200 50300 4
{
T 48100 50350 5 10 1 1 0 0 1
netname=RAM_D[01]
}
N 47800 50000 49200 50000 4
{
T 48100 50050 5 10 1 1 0 0 1
netname=RAM_D[02]
}
N 47800 49700 49200 49700 4
{
T 48100 49750 5 10 1 1 0 0 1
netname=RAM_D[03]
}
N 47800 49400 49200 49400 4
{
T 48100 49450 5 10 1 1 0 0 1
netname=RAM_D[04]
}
N 47800 49100 49200 49100 4
{
T 48100 49150 5 10 1 1 0 0 1
netname=RAM_D[05]
}
N 47800 48800 49200 48800 4
{
T 48100 48850 5 10 1 1 0 0 1
netname=RAM_D[06]
}
N 47800 48500 49200 48500 4
{
T 48100 48550 5 10 1 1 0 0 1
netname=RAM_D[07]
}
N 47800 48200 49200 48200 4
{
T 48100 48250 5 10 1 1 0 0 1
netname=RAM_D[08]
}
N 47800 47900 49200 47900 4
{
T 48100 47950 5 10 1 1 0 0 1
netname=RAM_D[09]
}
N 47800 47600 49200 47600 4
{
T 48100 47650 5 10 1 1 0 0 1
netname=RAM_D[10]
}
N 47800 47300 49200 47300 4
{
T 48100 47350 5 10 1 1 0 0 1
netname=RAM_D[11]
}
N 47800 47000 49200 47000 4
{
T 48100 47050 5 10 1 1 0 0 1
netname=RAM_D[12]
}
N 47800 46700 49200 46700 4
{
T 48100 46750 5 10 1 1 0 0 1
netname=RAM_D[13]
}
N 47800 46400 49200 46400 4
{
T 48100 46450 5 10 1 1 0 0 1
netname=RAM_D[14]
}
N 47800 46100 49200 46100 4
{
T 48100 46150 5 10 1 1 0 0 1
netname=RAM_D[15]
}
N 47200 54100 47500 54100 4
N 47500 53800 47200 53800 4
N 47200 53500 47500 53500 4
N 47200 53200 47500 53200 4
N 47200 52900 47500 52900 4
N 47200 52600 47500 52600 4
N 47200 52300 47500 52300 4
C 47400 51800 1 0 0 gnd-1.sym
N 47500 52100 47500 54100 4
C 48400 53500 1 90 0 capacitor-1.sym
{
T 47700 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 47900 53700 5 10 1 1 90 0 1
refdes=C401
T 47500 53700 5 10 0 0 90 0 1
symversion=0.1
T 48400 53500 5 10 0 0 90 0 1
footprint=0805
T 48500 53700 5 10 1 1 90 2 1
value=100nF
}
C 49400 53500 1 90 0 capacitor-1.sym
{
T 48700 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 48900 53700 5 10 1 1 90 0 1
refdes=C402
T 48500 53700 5 10 0 0 90 0 1
symversion=0.1
T 49400 53500 5 10 0 0 90 0 1
footprint=0805
T 49500 53700 5 10 1 1 90 2 1
value=100nF
}
C 50400 53500 1 90 0 capacitor-1.sym
{
T 49700 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 49900 53700 5 10 1 1 90 0 1
refdes=C403
T 49500 53700 5 10 0 0 90 0 1
symversion=0.1
T 50400 53500 5 10 0 0 90 0 1
footprint=0805
T 50500 53700 5 10 1 1 90 2 1
value=100nF
}
C 51400 53500 1 90 0 capacitor-1.sym
{
T 50700 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 50900 53700 5 10 1 1 90 0 1
refdes=C404
T 50500 53700 5 10 0 0 90 0 1
symversion=0.1
T 51400 53500 5 10 0 0 90 0 1
footprint=0805
T 51500 53700 5 10 1 1 90 2 1
value=100nF
}
N 47200 56500 48200 56500 4
N 47200 56200 49200 56200 4
N 49200 56200 49200 54400 4
N 47200 55900 50200 55900 4
N 50200 55900 50200 54400 4
N 47200 55600 51200 55600 4
N 51200 55600 51200 54400 4
C 52400 53500 1 90 0 capacitor-1.sym
{
T 51700 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 51900 53700 5 10 1 1 90 0 1
refdes=C405
T 51500 53700 5 10 0 0 90 0 1
symversion=0.1
T 52400 53500 5 10 0 0 90 0 1
footprint=0805
T 52500 53700 5 10 1 1 90 2 1
value=100nF
}
N 47200 55300 52200 55300 4
N 52200 55300 52200 54400 4
C 53400 53500 1 90 0 capacitor-1.sym
{
T 52700 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 52900 53700 5 10 1 1 90 0 1
refdes=C406
T 52500 53700 5 10 0 0 90 0 1
symversion=0.1
T 53400 53500 5 10 0 0 90 0 1
footprint=0805
T 53500 53700 5 10 1 1 90 2 1
value=100nF
}
C 54400 53500 1 90 0 capacitor-1.sym
{
T 53700 53700 5 10 0 0 90 0 1
device=CAPACITOR
T 53900 53700 5 10 1 1 90 0 1
refdes=C407
T 53500 53700 5 10 0 0 90 0 1
symversion=0.1
T 54400 53500 5 10 0 0 90 0 1
footprint=0805
T 54500 53700 5 10 1 1 90 2 1
value=100nF
}
N 47200 55000 53200 55000 4
N 53200 55000 53200 54400 4
N 47200 54700 54200 54700 4
N 54200 54700 54200 54400 4
C 48100 53000 1 0 0 gnd-1.sym
N 48200 53500 48200 53300 4
N 49200 53500 49200 53300 4
C 49100 53000 1 0 0 gnd-1.sym
N 50200 53500 50200 53300 4
C 50100 53000 1 0 0 gnd-1.sym
N 51200 53500 51200 53300 4
C 51100 53000 1 0 0 gnd-1.sym
N 52200 53500 52200 53300 4
C 52100 53000 1 0 0 gnd-1.sym
N 53200 53500 53200 53300 4
C 53100 53000 1 0 0 gnd-1.sym
N 54200 53500 54200 53300 4
C 54100 53000 1 0 0 gnd-1.sym
C 48000 56500 1 0 0 generic-power.sym
{
T 48200 56750 5 10 1 1 0 3 1
net=+3.125V:1
}
N 48200 56200 48200 56500 4
N 48200 56200 48200 55900 4
N 48200 55900 48200 55600 4
N 48200 55600 48200 55300 4
N 48200 55300 48200 55000 4
N 48200 55000 48200 54700 4
N 48200 54700 48200 54400 4
N 47200 61600 48525 61600 4
{
T 47300 61650 5 10 1 1 0 0 1
netname=RAM_D[00]
}
N 47200 61300 48525 61300 4
{
T 47300 61350 5 10 1 1 0 0 1
netname=RAM_D[01]
}
N 47200 61000 48525 61000 4
{
T 47300 61050 5 10 1 1 0 0 1
netname=RAM_D[02]
}
N 47200 60700 48525 60700 4
{
T 47300 60750 5 10 1 1 0 0 1
netname=RAM_D[03]
}
N 47200 60400 48525 60400 4
{
T 47300 60450 5 10 1 1 0 0 1
netname=RAM_D[04]
}
N 47200 60100 48525 60100 4
{
T 47300 60150 5 10 1 1 0 0 1
netname=RAM_D[05]
}
N 47200 59800 48525 59800 4
{
T 47300 59850 5 10 1 1 0 0 1
netname=RAM_D[06]
}
N 47200 59500 48525 59500 4
{
T 47300 59550 5 10 1 1 0 0 1
netname=RAM_D[07]
}
N 47200 59200 48525 59200 4
{
T 47300 59250 5 10 1 1 0 0 1
netname=RAM_D[08]
}
N 47200 58900 48525 58900 4
{
T 47300 58950 5 10 1 1 0 0 1
netname=RAM_D[09]
}
N 47200 58600 48525 58600 4
{
T 47300 58650 5 10 1 1 0 0 1
netname=RAM_D[10]
}
N 47200 58300 48525 58300 4
{
T 47300 58350 5 10 1 1 0 0 1
netname=RAM_D[11]
}
N 47200 58000 48525 58000 4
{
T 47300 58050 5 10 1 1 0 0 1
netname=RAM_D[12]
}
N 47200 57700 48525 57700 4
{
T 47300 57750 5 10 1 1 0 0 1
netname=RAM_D[13]
}
N 47200 57400 48525 57400 4
{
T 47300 57450 5 10 1 1 0 0 1
netname=RAM_D[14]
}
N 47200 57100 48525 57100 4
{
T 47300 57150 5 10 1 1 0 0 1
netname=RAM_D[15]
}
N 43400 61600 42000 61600 4
{
T 43300 61650 5 10 1 1 0 6 1
netname=RAM_A[00]
}
N 43400 61300 42000 61300 4
{
T 43300 61350 5 10 1 1 0 6 1
netname=RAM_A[01]
}
N 43400 61000 42000 61000 4
{
T 43300 61050 5 10 1 1 0 6 1
netname=RAM_A[02]
}
N 43400 60700 42000 60700 4
{
T 43300 60750 5 10 1 1 0 6 1
netname=RAM_A[03]
}
N 43400 60400 42000 60400 4
{
T 43300 60450 5 10 1 1 0 6 1
netname=RAM_A[04]
}
N 43400 60100 42000 60100 4
{
T 43300 60150 5 10 1 1 0 6 1
netname=RAM_A[05]
}
N 43400 59800 42000 59800 4
{
T 43300 59850 5 10 1 1 0 6 1
netname=RAM_A[06]
}
N 43400 59500 42000 59500 4
{
T 43300 59550 5 10 1 1 0 6 1
netname=RAM_A[07]
}
N 43400 59200 42000 59200 4
{
T 43300 59250 5 10 1 1 0 6 1
netname=RAM_A[08]
}
N 43400 58900 42000 58900 4
{
T 43300 58950 5 10 1 1 0 6 1
netname=RAM_A[09]
}
N 43400 58600 42000 58600 4
{
T 43300 58650 5 10 1 1 0 6 1
netname=RAM_A[10]
}
N 43400 58300 42000 58300 4
{
T 43300 58350 5 10 1 1 0 6 1
netname=RAM_A[11]
}
N 43400 58000 42000 58000 4
{
T 43300 58050 5 10 1 1 0 6 1
netname=RAM_A[12]
}
N 43400 57400 42000 57400 4
{
T 43300 57450 5 10 1 1 0 6 1
netname=RAM_A[13]
}
N 43400 57100 42000 57100 4
{
T 43300 57150 5 10 1 1 0 6 1
netname=RAM_A[14]
}
N 41800 54400 43400 54400 4
{
T 43300 54450 5 10 1 1 0 6 1
netname=RAM_DQM[0]
}
N 41800 54100 43400 54100 4
{
T 43300 54150 5 10 1 1 0 6 1
netname=RAM_DQM[1]
}
N 41800 55000 43400 55000 4
{
T 43300 55050 5 10 1 1 0 6 1
netname=RAM_CKE
}
N 41800 55300 43400 55300 4
{
T 43300 55350 5 10 1 1 0 6 1
netname=RAM_CLK
}
N 41800 53500 43400 53500 4
{
T 43300 53550 5 10 1 1 0 6 1
netname=RAM_CAS_N
}
N 41800 53200 43400 53200 4
{
T 43300 53250 5 10 1 1 0 6 1
netname=RAM_RAS_N
}
N 41800 52600 43400 52600 4
{
T 43300 52650 5 10 1 1 0 6 1
netname=RAM_WR_N
}
N 41800 52300 43400 52300 4
{
T 43300 52350 5 10 1 1 0 6 1
netname=RAM_CS_N
}
N 41700 45200 43400 45200 4
{
T 43000 45250 5 10 1 1 0 6 1
netname=RAM_DQM[2]
}
N 41700 44900 43400 44900 4
{
T 43000 44950 5 10 1 1 0 6 1
netname=RAM_DQM[3]
}
N 47800 45800 49200 45800 4
{
T 48100 45850 5 10 1 1 0 0 1
netname=RAM_D[16]
}
N 47800 45500 49200 45500 4
{
T 48100 45550 5 10 1 1 0 0 1
netname=RAM_D[17]
}
N 47800 45200 49200 45200 4
{
T 48100 45250 5 10 1 1 0 0 1
netname=RAM_D[18]
}
N 47800 44900 49200 44900 4
{
T 48100 44950 5 10 1 1 0 0 1
netname=RAM_D[19]
}
N 47800 44600 49200 44600 4
{
T 48100 44650 5 10 1 1 0 0 1
netname=RAM_D[20]
}
N 47800 44300 49200 44300 4
{
T 48100 44350 5 10 1 1 0 0 1
netname=RAM_D[21]
}
N 47800 44000 49200 44000 4
{
T 48100 44050 5 10 1 1 0 0 1
netname=RAM_D[22]
}
N 47800 43700 49200 43700 4
{
T 48100 43750 5 10 1 1 0 0 1
netname=RAM_D[23]
}
N 47800 43400 49200 43400 4
{
T 48100 43450 5 10 1 1 0 0 1
netname=RAM_D[24]
}
N 47800 43100 49200 43100 4
{
T 48100 43150 5 10 1 1 0 0 1
netname=RAM_D[25]
}
N 47800 42800 49200 42800 4
{
T 48100 42850 5 10 1 1 0 0 1
netname=RAM_D[26]
}
N 47800 42500 49200 42500 4
{
T 48100 42550 5 10 1 1 0 0 1
netname=RAM_D[27]
}
N 47800 42200 49200 42200 4
{
T 48100 42250 5 10 1 1 0 0 1
netname=RAM_D[28]
}
N 47800 41900 49200 41900 4
{
T 48100 41950 5 10 1 1 0 0 1
netname=RAM_D[29]
}
N 47800 41600 49200 41600 4
{
T 48100 41650 5 10 1 1 0 0 1
netname=RAM_D[30]
}
N 47800 41300 49200 41300 4
{
T 48100 41350 5 10 1 1 0 0 1
netname=RAM_D[31]
}
C 57300 52000 1 0 0 MT48LC16M16A2.sym
{
T 57600 62200 5 10 1 1 0 0 1
footprint=TSOPII54
T 57600 62000 5 10 1 1 0 0 1
device=MT48LC16M16A2P-7E
T 57600 62400 5 10 1 1 0 0 1
refdes=U403
}
C 43400 52000 1 0 0 MT48LC16M16A2.sym
{
T 43700 62200 5 10 1 1 0 0 1
footprint=TSOPII54
T 43700 62000 5 10 1 1 0 0 1
device=MT48LC16M16A2P-7E
T 43700 62400 5 10 1 1 0 0 1
refdes=U401
}
C 43200 41000 1 0 0 LPC3180-RAM.sym
{
T 43700 51200 5 10 1 1 0 0 1
footprint=SOT824
T 43700 51000 5 10 1 1 0 0 1
device=LPC3180FEL320
T 43700 51400 5 10 1 1 0 0 1
refdes=U402
}
T 65300 41700 9 10 1 0 0 0 1
Need to do some research how the RAM_CLKIN feedback input works