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v 20060123 1
B 300 300 3800 9900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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uselicense=unlimited
T 4100 10500 9 10 0 0 0 0 1
distlicense=GPL (v2 or any later version)
T 4100 10700 9 10 0 0 0 0 1
copyright=2008 Tibor Palinkas
T 4100 10900 9 10 0 0 0 0 1
author=Tibor Palinkas
T 4100 11100 9 10 0 0 0 0 1
description=NXP 16/32-bit ARM926EJ-S microcontroller
T 4100 11300 9 10 0 0 0 0 1
documentation=http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc3180.01.pdf
T 300 10300 5 10 1 1 0 0 1
block=RAM
T 300 10500 5 10 1 1 0 0 1
device=LPC3180FEL320
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footprint=SOT824
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refdes=U?
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{
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pinlabel=RAM_A[09]
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pinnumber=AA23
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pinseq=AA23
}
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{
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pinlabel=RAM_A[00]
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pinnumber=AD22
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pinseq=AD22
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pinlabel=RAM_D[21]
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pinnumber=H24
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pinseq=H24
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{
T 350 6300 9 10 1 1 0 1 1
pinlabel=RAM_A[12]
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pinnumber=Y23
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pinseq=Y23
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{
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pinlabel=RAM_CAS_N
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pinnumber=V23
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pinseq=V23
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{
T 4050 2100 9 10 1 1 0 7 1
pinlabel=RAM_D[26]
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pinnumber=H23
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pinseq=H23
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{
T 4050 5700 9 10 1 1 0 7 1
pinlabel=RAM_D[14]
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pinnumber=M23
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pinseq=M23
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{
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pinlabel=RAM_CLKIN
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pinnumber=T21
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pinseq=T21
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{
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pinlabel=RAM_D[05]
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pinnumber=R23
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pinseq=R23
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T 4050 9900 9 10 1 1 0 7 1
pinlabel=RAM_D[00]
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pinnumber=T23
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pinseq=T23
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pinlabel=RAM_A[10]
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pinnumber=Y22
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pinseq=Y22
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P 0 4500 300 4500 1 0 0
{
T 350 4500 9 10 1 1 0 1 1
pinlabel=RAM_DQM[2]
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pinnumber=V21
T 200 4550 5 8 0 1 0 6 1
pinseq=V21
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P 4400 4200 4100 4200 1 0 0
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T 4050 4200 9 10 1 1 0 7 1
pinlabel=RAM_D[19]
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pinnumber=H21
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pinseq=H21
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{
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pinlabel=RAM_D[31]
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pinnumber=E24
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pinseq=E24
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P 4400 8700 4100 8700 1 0 0
{
T 4050 8700 9 10 1 1 0 7 1
pinlabel=RAM_D[04]
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pinnumber=P21
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pinseq=P21
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P 4400 2400 4100 2400 1 0 0
{
T 4050 2400 9 10 1 1 0 7 1
pinlabel=RAM_D[25]
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pinnumber=J21
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pinseq=J21
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T 350 3300 9 10 1 1 0 1 1
pinlabel=RAM_RAS_N
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pinnumber=U21
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pinseq=U21
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T 350 6000 9 10 1 1 0 1 1
pinlabel=RAM_A[13]
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pinnumber=AA24
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pinseq=AA24
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P 4400 1200 4100 1200 1 0 0
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T 4050 1200 9 10 1 1 0 7 1
pinlabel=RAM_D[29]
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pinnumber=F21
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pinseq=F21
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T 350 2100 9 10 1 1 0 1 1
pinlabel=RAM_CKE
T 200 2150 5 8 1 1 0 6 1
pinnumber=U24
T 200 2150 5 8 0 1 0 6 1
pinseq=U24
}
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{
T 350 2400 9 10 1 1 0 1 1
pinlabel=RAM_CLK
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pinnumber=U23
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pinseq=U23
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P 0 9000 300 9000 1 0 0
{
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pinnumber=AD24
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pinseq=AD24
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{
T 350 8700 9 10 1 1 0 1 1
pinlabel=RAM_A[04]
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pinnumber=AC22
T 200 8750 5 8 0 1 0 6 1
pinseq=AC22
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P 4400 2700 4100 2700 1 0 0
{
T 4050 2700 9 10 1 1 0 7 1
pinlabel=RAM_D[24]
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pinnumber=G23
T 4200 2750 5 8 0 1 0 0 1
pinseq=G23
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{
T 4050 5400 9 10 1 1 0 7 1
pinlabel=RAM_D[15]
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pinnumber=L24
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pinseq=L24
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P 0 4200 300 4200 1 0 0
{
T 350 4200 9 10 1 1 0 1 1
pinlabel=RAM_DQM[3]
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pinnumber=W24
T 200 4250 5 8 0 1 0 6 1
pinseq=W24
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pinseq=E23
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{
T 4050 7800 9 10 1 1 0 7 1
pinlabel=RAM_D[08]
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pinnumber=P23
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pinseq=P23
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P 0 7800 300 7800 1 0 0
{
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pinlabel=RAM_A[07]
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pinnumber=AB22
T 200 7850 5 8 0 1 0 6 1
pinseq=AB22
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pinseq=L22
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T 4050 7500 9 10 1 1 0 7 1
pinlabel=RAM_D[07]
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pinseq=N21
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T 4050 9300 9 10 1 1 0 7 1
pinlabel=RAM_D[02]
T 4200 9350 5 8 1 1 0 0 1
pinnumber=T24
T 4200 9350 5 8 0 1 0 0 1
pinseq=T24
}
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{
T 350 5100 9 10 1 1 0 1 1
pinlabel=RAM_DQM[0]
T 200 5150 5 8 1 1 0 6 1
pinnumber=Y24
T 200 5150 5 8 0 1 0 6 1
pinseq=Y24
}
P 0 5700 300 5700 1 0 0
{
T 350 5700 9 10 1 1 0 1 1
pinlabel=RAM_A[14]
T 200 5750 5 8 1 1 0 6 1
pinnumber=W21
T 200 5750 5 8 0 1 0 6 1
pinseq=W21
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P 4400 6300 4100 6300 1 0 0
{
T 4050 6300 9 10 1 1 0 7 1
pinlabel=RAM_D[12]
T 4200 6350 5 8 1 1 0 0 1
pinnumber=M24
T 4200 6350 5 8 0 1 0 0 1
pinseq=M24
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T 4050 1800 9 10 1 1 0 7 1
pinlabel=RAM_D[27]
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pinnumber=G24
T 4200 1850 5 8 0 1 0 0 1
pinseq=G24
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P 0 8400 300 8400 1 0 0
{
T 350 8400 9 10 1 1 0 1 1
pinlabel=RAM_A[05]
T 200 8450 5 8 1 1 0 6 1
pinnumber=AA21
T 200 8450 5 8 0 1 0 6 1
pinseq=AA21
}
P 4400 5100 4100 5100 1 0 0
{
T 4050 5100 9 10 1 1 0 7 1
pinlabel=RAM_D[16]/DDR_DQS0
T 4200 5150 5 8 1 1 0 0 1
pinnumber=L23
T 4200 5150 5 8 0 1 0 0 1
pinseq=L23
}
P 4400 9000 4100 9000 1 0 0
{
T 4050 9000 9 10 1 1 0 7 1
pinlabel=RAM_D[03]
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pinnumber=R24
T 4200 9050 5 8 0 1 0 0 1
pinseq=R24
}
P 0 9600 300 9600 1 0 0
{
T 350 9600 9 10 1 1 0 1 1
pinlabel=RAM_A[01]
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pinnumber=AB20
T 200 9650 5 8 0 1 0 6 1
pinseq=AB20
}
P 4400 1500 4100 1500 1 0 0
{
T 4050 1500 9 10 1 1 0 7 1
pinlabel=RAM_D[28]
T 4200 1550 5 8 1 1 0 0 1
pinnumber=F24
T 4200 1550 5 8 0 1 0 0 1
pinseq=F24
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{
T 350 8100 9 10 1 1 0 1 1
pinlabel=RAM_A[06]
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pinnumber=AC23
T 200 8150 5 8 0 1 0 6 1
pinseq=AC23
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{
T 4050 6600 9 10 1 1 0 7 1
pinlabel=RAM_D[11]
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pinnumber=N23
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pinseq=N23
}
P 4400 7200 4100 7200 1 0 0
{
T 4050 7200 9 10 1 1 0 7 1
pinlabel=RAM_D[09]
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pinnumber=N24
T 4200 7250 5 8 0 1 0 0 1
pinseq=N24
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P 0 9300 300 9300 1 0 0
{
T 350 9300 9 10 1 1 0 1 1
pinlabel=RAM_A[02]
T 200 9350 5 8 1 1 0 6 1
pinnumber=AD23
T 200 9350 5 8 0 1 0 6 1
pinseq=AD23
}
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{
T 350 4800 9 10 1 1 0 1 1
pinlabel=RAM_DQM[1]
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pinnumber=W23
T 200 4850 5 8 0 1 0 6 1
pinseq=W23
}
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{
T 4050 6900 9 10 1 1 0 7 1
pinlabel=RAM_D[10]
T 4200 6950 5 8 1 1 0 0 1
pinnumber=M22
T 4200 6950 5 8 0 1 0 0 1
pinseq=M22
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P 4400 4500 4100 4500 1 0 0
{
T 4050 4500 9 10 1 1 0 7 1
pinlabel=RAM_D[18]/DDR_NCLK
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pinnumber=K24
T 4200 4550 5 8 0 1 0 0 1
pinseq=K24
}
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{
T 4050 3900 9 10 1 1 0 7 1
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pinseq=J24
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P 0 7500 300 7500 1 0 0
{
T 350 7500 9 10 1 1 0 1 1
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P 0 6600 300 6600 1 0 0
{
T 350 6600 9 10 1 1 0 1 1
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T 200 6650 5 8 1 1 0 6 1
pinnumber=AB24
T 200 6650 5 8 0 1 0 6 1
pinseq=AB24
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{
T 4050 3000 9 10 1 1 0 7 1
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pinnumber=H22
T 4200 3050 5 8 0 1 0 0 1
pinseq=H22
}
P 0 1200 300 1200 1 0 0
{
T 350 1200 9 10 1 1 0 1 1
pinlabel=RAM_CS_N
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T 200 1250 5 8 0 1 0 6 1
pinseq=V24
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{
T 4050 4800 9 10 1 1 0 7 1
pinlabel=RAM_D[17]/DDR_DQS1
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{
T 4050 8100 9 10 1 1 0 7 1
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T 4200 8150 5 8 0 1 0 0 1
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}
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{
T 4050 9600 9 10 1 1 0 7 1
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pinseq=T22
}
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{
T 4050 3300 9 10 1 1 0 7 1
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pinseq=K23
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{
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pinnumber=V22
T 200 1550 5 8 0 1 0 6 1
pinseq=V22
}